diff options
Diffstat (limited to 'debug/targets/RISC-V')
-rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 31 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 13 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64-2-hwthread.py | 13 |
3 files changed, 57 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg new file mode 100644 index 0000000..df4a501 --- /dev/null +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -0,0 +1,31 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME_0 $_CHIPNAME.cpu0 +set _TARGETNAME_1 $_CHIPNAME.cpu1 +target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread +#target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread +target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 +target smp $_TARGETNAME_0 $_TARGETNAME_1 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 +riscv expose_custom 1,12345-12348 + +init + +set challenge [ocd_riscv authdata_read] +riscv authdata_write [expr $challenge + 1] + +halt diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py new file mode 100644 index 0000000..bec68dc --- /dev/null +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -0,0 +1,13 @@ +import targets +import testlib + +import spike32 # pylint: disable=import-error + +class spike32_2(targets.Target): + harts = [spike32.spike32_hart(), spike32.spike32_hart()] + openocd_config_path = "spike-2-hwthread.cfg" + timeout_sec = 5 + implements_custom_test = True + + def create(self): + return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py new file mode 100644 index 0000000..e57f490 --- /dev/null +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -0,0 +1,13 @@ +import targets +import testlib + +import spike64 # pylint: disable=import-error + +class spike64_2(targets.Target): + harts = [spike64.spike64_hart(), spike64.spike64_hart()] + openocd_config_path = "spike-2-hwthread.cfg" + timeout_sec = 5 + implements_custom_test = True + + def create(self): + return testlib.Spike(self) |