diff options
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 4 |
3 files changed, 12 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index fc20b53..7607b46 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -12,5 +12,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 17526ec..c78cf8f 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -15,5 +15,9 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 799e3cb..5a70f52 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -13,5 +13,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt |