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-rw-r--r--debug/targets/RISC-V/spike32.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index a831ecb..e633eea 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -17,4 +17,4 @@ class spike32(targets.Target):
def create(self):
# 64-bit FPRs on 32-bit target
- return testlib.Spike(self, isa="RV32IMAFDC")
+ return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4)