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authorYunsup Lee <yunsup@cs.berkeley.edu>2014-11-12 23:09:10 -0800
committerYunsup Lee <yunsup@cs.berkeley.edu>2014-11-12 23:09:10 -0800
commitedbd1cfa27faa0b5fe51e4708f4fce102a512b16 (patch)
treea78d917b49edeeddaebf1f91ead4c327c5d63d09 /isa
parent8d6a0e0da4c228659077e56fc3988e6b3d321dc4 (diff)
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beef up rv32si tests
Diffstat (limited to 'isa')
-rw-r--r--isa/rv32si/Makefrag10
-rw-r--r--isa/rv32si/fa_addr_zscale_8192.S90
-rw-r--r--isa/rv32si/fa_fetch_zscale_8192.S47
-rw-r--r--isa/rv32si/illegal.S41
-rw-r--r--isa/rv32si/ipi_zscale.S48
-rw-r--r--isa/rv32si/ma_addr.S87
-rw-r--r--isa/rv32si/ma_fetch.S56
-rw-r--r--isa/rv32si/privileged.S38
-rw-r--r--isa/rv32si/sbreak.S41
-rw-r--r--isa/rv32si/scall.S41
-rw-r--r--isa/rv32si/timer.S48
11 files changed, 547 insertions, 0 deletions
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 7ffc060..6a53e7f 100644
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -5,6 +5,16 @@
rv32si_sc_tests = \
csr \
shamt \
+ ma_fetch \
+ fa_fetch_zscale_8192 \
+ illegal \
+ privileged \
+ scall \
+ sbreak \
+ ma_addr \
+ fa_addr_zscale_8192 \
+ timer \
+ ipi_zscale \
rv32si_mc_tests = \
ipi \
diff --git a/isa/rv32si/fa_addr_zscale_8192.S b/isa/rv32si/fa_addr_zscale_8192.S
new file mode 100644
index 0000000..8bb110a
--- /dev/null
+++ b/isa/rv32si/fa_addr_zscale_8192.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# fa_addr.S
+#-----------------------------------------------------------------------------
+#
+# Test fault load/store trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ li s0, 0x2000
+ li s1, 1
+
+loop:
+ addi s1, s1, -1
+
+ la t0, evec_load
+ csrw evec, t0
+
+ li TESTNUM, 2
+ lw x0, 0(s0)
+ j fail
+
+ li TESTNUM, 3
+ lh x0, 0(s0)
+ j fail
+
+ li TESTNUM, 4
+ lhu x0, 0(s0)
+ j fail
+
+ li TESTNUM, 5
+ lb x0, 0(s0)
+ j fail
+
+ li TESTNUM, 6
+ lbu x0, 0(s0)
+ j fail
+
+ la t0, evec_store
+ csrw evec, t0
+
+ li TESTNUM, 7
+ sw x0, 0(s0)
+ j fail
+
+ li TESTNUM, 8
+ sh x0, 0(s0)
+ j fail
+
+ li TESTNUM, 9
+ sb x0, 0(s0)
+ j fail
+
+ li s0, 0xbad1dea0
+ beq s1, x0, loop
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec_load:
+ li t1, CAUSE_FAULT_LOAD
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+evec_store:
+ li t1, CAUSE_FAULT_STORE
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/fa_fetch_zscale_8192.S b/isa/rv32si/fa_fetch_zscale_8192.S
new file mode 100644
index 0000000..b7cde4e
--- /dev/null
+++ b/isa/rv32si/fa_fetch_zscale_8192.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# fa_fetch.S
+#-----------------------------------------------------------------------------
+#
+# Test fault fetch trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ li TESTNUM, 2
+ li t0, 0x2000
+ jr t0
+ j fail
+
+ li TESTNUM, 3
+ li t0, 0xcafebabc
+ jr t0
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, CAUSE_FAULT_FETCH
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S
new file mode 100644
index 0000000..68451a9
--- /dev/null
+++ b/isa/rv32si/illegal.S
@@ -0,0 +1,41 @@
+#*****************************************************************************
+# illegal.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ li TESTNUM, 2
+ .word 0
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, CAUSE_ILLEGAL_INSTRUCTION
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/ipi_zscale.S b/isa/rv32si/ipi_zscale.S
new file mode 100644
index 0000000..5f1106b
--- /dev/null
+++ b/isa/rv32si/ipi_zscale.S
@@ -0,0 +1,48 @@
+#*****************************************************************************
+# ipi.S
+#-----------------------------------------------------------------------------
+#
+# Test ipi interrupt.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ csrw clear_ipi, x0
+ li t1, 1<<21
+ csrs status, t1 # turn on timer IRQ 5
+ csrsi status, 4 # enable interrupts
+
+ li t1,1
+ csrw send_ipi, t1
+
+ li TESTNUM, 2
+ li a0,1000
+loop:
+ div x0, x0, x0
+ addi a0, a0, -1
+ bne a0, x0, loop
+ j fail # assumption is that you will get an ipi before this loop ends
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, 0x80000000|IRQ_IPI
+ csrr t0, cause
+ bne t0, t1, fail
+ j pass
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S
new file mode 100644
index 0000000..8081411
--- /dev/null
+++ b/isa/rv32si/ma_addr.S
@@ -0,0 +1,87 @@
+#*****************************************************************************
+# ma_addr.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ld/st trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la s0, evec_load
+
+ la t0, evec_load
+ csrw evec, t0
+
+ li TESTNUM, 2
+ lw x0, 1(s0)
+ j fail
+
+ li TESTNUM, 3
+ lw x0, 2(s0)
+ j fail
+
+ li TESTNUM, 4
+ lw x0, 3(s0)
+ j fail
+
+ li TESTNUM, 5
+ lh x0, 1(s0)
+ j fail
+
+ li TESTNUM, 6
+ lhu x0, 1(s0)
+ j fail
+
+ la t0, evec_store
+ csrw evec, t0
+
+ li TESTNUM, 7
+ sw x0, 1(s0)
+ j fail
+
+ li TESTNUM, 8
+ sw x0, 2(s0)
+ j fail
+
+ li TESTNUM, 9
+ sw x0, 3(s0)
+ j fail
+
+ li TESTNUM, 10
+ sh x0, 1(s0)
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec_load:
+ li t1, CAUSE_MISALIGNED_LOAD
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+evec_store:
+ li t1, CAUSE_MISALIGNED_STORE
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S
new file mode 100644
index 0000000..99302fb
--- /dev/null
+++ b/isa/rv32si/ma_fetch.S
@@ -0,0 +1,56 @@
+#*****************************************************************************
+# ma_fetch.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned fetch trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ li TESTNUM, 2
+ la t0, evec
+ jr t0, 2
+ j fail
+
+ li TESTNUM, 3
+ la t0, next
+ jr t0, 1
+ // this test should pass, since the low bit should be masked off
+
+next:
+ li TESTNUM, 4
+ la t0, evec
+ jr t0, 3
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec:
+ li t0, 3
+ beq TESTNUM, t0, fail
+
+ li t1, CAUSE_MISALIGNED_FETCH
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/privileged.S b/isa/rv32si/privileged.S
new file mode 100644
index 0000000..d827bf5
--- /dev/null
+++ b/isa/rv32si/privileged.S
@@ -0,0 +1,38 @@
+#*****************************************************************************
+# privileged.S
+#-----------------------------------------------------------------------------
+#
+# Test privileged instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ csrci status, 1
+
+ li TESTNUM, 2
+ sret
+ j fail
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, CAUSE_PRIVILEGED_INSTRUCTION
+ csrr t0, cause
+ bne t0, t1, fail
+ j pass
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/sbreak.S b/isa/rv32si/sbreak.S
new file mode 100644
index 0000000..645822d
--- /dev/null
+++ b/isa/rv32si/sbreak.S
@@ -0,0 +1,41 @@
+#*****************************************************************************
+# scall.S
+#-----------------------------------------------------------------------------
+#
+# Test syscall trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ li TESTNUM, 2
+ sbreak
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, CAUSE_BREAKPOINT
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S
new file mode 100644
index 0000000..608596d
--- /dev/null
+++ b/isa/rv32si/scall.S
@@ -0,0 +1,41 @@
+#*****************************************************************************
+# scall.S
+#-----------------------------------------------------------------------------
+#
+# Test syscall trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ li TESTNUM, 2
+ scall
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, CAUSE_SYSCALL
+ csrr t0, cause
+ bne t0, t1, fail
+ csrr t0, epc
+ addi t0, t0, 8
+ csrw epc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
new file mode 100644
index 0000000..d46c2fd
--- /dev/null
+++ b/isa/rv32si/timer.S
@@ -0,0 +1,48 @@
+#*****************************************************************************
+# timer.S
+#-----------------------------------------------------------------------------
+#
+# Test timer interrupt.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+ la t0, evec
+ csrw evec, t0
+
+ csrr t0, count
+ add t0, t0, 1000
+ csrw compare, t0
+
+ li t1, 1<<23
+ csrs status, t1 # turn on timer IRQ 7
+ csrsi status, 4 # enable interrupts
+
+ li TESTNUM, 2
+ li a0,1000
+loop:
+ div x0, x0, x0
+ addi a0, a0, -1
+ bne a0, x0, loop
+ j fail # assumption is that you can't divide in one cycle
+
+ TEST_PASSFAIL
+
+evec:
+ li t1, 0x80000000|IRQ_TIMER
+ csrr t0, cause
+ bne t0, t1, fail
+ j pass
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END