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authorAndrew Waterman <andrew@sifive.com>2017-03-30 00:30:29 -0700
committerAndrew Waterman <andrew@sifive.com>2017-03-30 00:30:29 -0700
commitc066a09ce18eb9252892d105386b40fa80242120 (patch)
tree8b4258cd60f1813ff0189df45fbf3524014d62f0 /isa
parentf84441c926756579f2108f6e3ab17e54c24954ed (diff)
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Expand dirty-bit test to test MPRV and SUM
Diffstat (limited to 'isa')
-rw-r--r--isa/rv64si/dirty.S57
1 files changed, 30 insertions, 27 deletions
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 86e4656..17aa57f 100644
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -13,40 +13,45 @@
RVTEST_RV64M
RVTEST_CODE_BEGIN
- # Turn on VM with superpage identity mapping
+ # Turn on VM
li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
- la a2, page_table_2
- srl a2, a2, RISCV_PGSHIFT
- or a2, a2, a0
csrw sptbr, a1
sfence.vma
- li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
+
+ # Set up MPRV with MPP=S, so loads and stores use S-mode
+ li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
csrs mstatus, a1
- la a1, 1f - DRAM_BASE
- csrw mepc, a1
- la a1, stvec_handler - DRAM_BASE
- csrw stvec, a1
- mret
-1:
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
- li t0, 1
- sw t0, dummy, t1
+ li t2, 1
+ sw t2, dummy - DRAM_BASE, t1
- # Load new page table
+ # Set SUM=1 so user memory access is permitted
li TESTNUM, 3
- csrw sptbr, a2
- sfence.vma
+ li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
+ csrs mstatus, a1
+
+ # Make sure SUM=1 works
+ lw t0, dummy - DRAM_BASE
+ bnez t0, die
# Try a non-faulting store to make sure dirty bit is set
- sw t0, dummy, t1
+ sw t2, dummy - DRAM_BASE, t1
+
+ # Make sure it succeeded
+ lw t0, dummy - DRAM_BASE
+ bne t0, t2, die
+
+ # Leave MPRV
+ li t0, MSTATUS_MPRV
+ csrc mstatus, t0
# Make sure D bit is set
- lw t0, page_table_2
+ lw t0, page_table_1
li t1, PTE_A | PTE_D
and t0, t0, t1
bne t0, t1, die
@@ -56,8 +61,8 @@ RVTEST_CODE_BEGIN
TEST_PASSFAIL
.align 2
-stvec_handler:
- csrr t0, scause
+mtvec_handler:
+ csrr t0, mcause
add t0, t0, -CAUSE_STORE_PAGE_FAULT
bnez t0, die
@@ -68,17 +73,17 @@ stvec_handler:
and t1, t0, PTE_D
bnez t1, die
skip:
- csrr t0, sepc
+ csrr t0, mepc
add t0, t0, 4
- csrw sepc, t0
- sret
+ csrw mepc, t0
+ mret
1:
li t1, 3
bne TESTNUM, t1, 1f
# The implementation doesn't appear to set D bits in HW. Skip the test,
# after making sure the D bit is clear.
- lw t0, page_table_2
+ lw t0, page_table_1
and t1, t0, PTE_D
bnez t1, die
j pass
@@ -95,9 +100,7 @@ RVTEST_DATA_BEGIN
TEST_DATA
.align 12
-page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_A
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
dummy: .dword 0
-.align 12
-page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W | PTE_A
RVTEST_DATA_END