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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
commit | 2f00c0c1f26a10f93f4a133bec69f4d0b95df685 (patch) | |
tree | 699ebd180e0de1076a2a511e5a2f133035dc8ca8 /isa/rv64sv/illegal_cfg_nfpr.S | |
parent | ddf8212714fcb6dc240a71bd1e1f52e02fc208b0 (diff) | |
download | riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.zip riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.gz riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.bz2 |
add hwacha exception support
Diffstat (limited to 'isa/rv64sv/illegal_cfg_nfpr.S')
-rw-r--r-- | isa/rv64sv/illegal_cfg_nfpr.S | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S new file mode 100644 index 0000000..b271268 --- /dev/null +++ b/isa/rv64sv/illegal_cfg_nfpr.S @@ -0,0 +1,102 @@ +#***************************************************************************** +# illegal_tvec_cmd.S +#----------------------------------------------------------------------------- +# +# Test illegal tvec command trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + setpcr status, SR_EI # enable interrupt + + la a3,handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status + + li a0,33 + slli a0,a0,6 + vsetcfg a0 + +vtcode2: + add x2,x2,x3 + stop + +handler: + vxcptkill + + li x28,2 + + # check cause + vxcptcause a3 + li a4,HWACHA_CAUSE_ILLEGAL_CFG + bne a3,a4,fail + + # check vec irq aux + vxcptaux a3 + li a4, 1 + bne a3,a4,fail + + # make sure vector unit has cleared out + vsetcfg 32,0 + li a3,4 + vsetvl a3,a3 + + la a3,src1 + la a4,src2 + vld vx2,a3 + vld vx3,a4 + lui a0,%hi(vtcode2) + vf %lo(vtcode2)(a0) + la a5,dest + vsd vx2,a5 + fence + + ld a1,0(a5) + li a2,5 + li x28,2 + bne a1,a2,fail + ld a1,8(a5) + li x28,3 + bne a1,a2,fail + ld a1,16(a5) + li x28,4 + bne a1,a2,fail + ld a1,24(a5) + li x28,5 + bne a1,a2,fail + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +src1: + .dword 1 + .dword 2 + .dword 3 + .dword 4 +src2: + .dword 4 + .dword 3 + .dword 2 + .dword 1 +dest: + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + +RVTEST_DATA_END |