diff options
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | env/hwacha_xcpt.h | 17 | ||||
| -rw-r--r-- | env/p/riscv_test.h | 1 | ||||
| -rw-r--r-- | env/pcr.h | 11 | ||||
| -rw-r--r-- | env/v/riscv_test.h | 1 | ||||
| -rw-r--r-- | env/v/vm.c | 4 | ||||
| -rw-r--r-- | isa/macros/scalar/test_macros.h | 40 | ||||
| -rw-r--r-- | isa/rv64sv/Makefrag | 5 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nfpr.S | 102 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nxpr.S | 101 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_inst.S (renamed from isa/rv64sv/illegal_tvec_cmd.S) | 34 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_tvec_regid.S | 18 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_vt_inst.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_vt_regid.S | 10 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utld.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utsd.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vld.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vsd.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vt_inst.S | 20 | ||||
| -rw-r--r-- | isa/rv64sv/privileged_inst.S | 105 |
20 files changed, 448 insertions, 122 deletions
@@ -5,4 +5,5 @@ *.dump *.out *.hex +.*.swp autom4te.cache diff --git a/env/hwacha_xcpt.h b/env/hwacha_xcpt.h new file mode 100644 index 0000000..5c4dacc --- /dev/null +++ b/env/hwacha_xcpt.h @@ -0,0 +1,17 @@ +#ifndef _HWACHA_XCPT_H +#define _HWACHA_XCPT_H + +#define HWACHA_CAUSE_ILLEGAL_CFG 0 // AUX: 0=illegal nxpr, 1=illegal nfpr +#define HWACHA_CAUSE_ILLEGAL_INSTRUCTION 1 // AUX: instruction +#define HWACHA_CAUSE_PRIVILEGED_INSTRUCTION 2 // AUX: instruction +#define HWACHA_CAUSE_TVEC_ILLEGAL_REGID 3 // AUX: instruction +#define HWACHA_CAUSE_VF_MISALIGNED_FETCH 4 // AUX: pc +#define HWACHA_CAUSE_VF_FAULT_FETCH 5 // AUX: pc +#define HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION 6 // AUX: pc +#define HWACHA_CAUSE_VF_ILLEGAL_REGID 7 // AUX: pc +#define HWACHA_CAUSE_MISALIGNED_LOAD 8 // AUX: badvaddr +#define HWACHA_CAUSE_MISALIGNED_STORE 9 // AUX: badvaddr +#define HWACHA_CAUSE_FAULT_LOAD 10 // AUX: badvaddr +#define HWACHA_CAUSE_FAULT_STORE 11 // AUX: badvaddr + +#endif diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h index 08af9dc..955afc0 100644 --- a/env/p/riscv_test.h +++ b/env/p/riscv_test.h @@ -2,6 +2,7 @@ #define _ENV_PHYSICAL_SINGLE_CORE_H #include "../pcr.h" +#include "../hwacha_xcpt.h" //----------------------------------------------------------------------- // Begin Macro @@ -59,17 +59,6 @@ #define CAUSE_MISALIGNED_STORE 9 #define CAUSE_FAULT_LOAD 10 #define CAUSE_FAULT_STORE 11 -#define CAUSE_VECTOR_DISABLED 12 -#define CAUSE_VECTOR_BANK 13 - -#define CAUSE_VECTOR_MISALIGNED_FETCH 24 -#define CAUSE_VECTOR_FAULT_FETCH 25 -#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26 -#define CAUSE_VECTOR_ILLEGAL_COMMAND 27 -#define CAUSE_VECTOR_MISALIGNED_LOAD 28 -#define CAUSE_VECTOR_MISALIGNED_STORE 29 -#define CAUSE_VECTOR_FAULT_LOAD 30 -#define CAUSE_VECTOR_FAULT_STORE 31 // page table entry (PTE) fields #define PTE_V 0x001 // Entry is a page Table descriptor diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h index 995db59..bfd5197 100644 --- a/env/v/riscv_test.h +++ b/env/v/riscv_test.h @@ -51,6 +51,7 @@ userstart: \ //----------------------------------------------------------------------- #include "../pcr.h" +#include "../hwacha_xcpt.h" #define vvcfg(nxregs, nfregs) ({ \ asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); }) @@ -201,9 +201,7 @@ void handle_trap(trapframe_t* tf) assert(0); tf->epc += 4; } - else if (tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE || - tf->cause == CAUSE_VECTOR_FAULT_LOAD || tf->cause == CAUSE_VECTOR_FAULT_STORE || - tf->cause == CAUSE_VECTOR_FAULT_FETCH) + else if (tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE) handle_fault(tf->badvaddr); else assert(0); diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 7da0b59..b856701 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -559,10 +559,11 @@ test_ ## testnum: \ #----------------------------------------------------------------------- -# RV64UV MACROS +# RV64SV MACROS #----------------------------------------------------------------------- -#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ +#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ + setpcr status, SR_EI; \ la a0, handler ## testnum; \ mtpcr a0, evec; \ vsetcfg nxreg, nfreg; \ @@ -574,13 +575,14 @@ test_ ## testnum: \ vld vx3, a1; \ lui a0,%hi(vtcode1 ## testnum); \ vf %lo(vtcode1 ## testnum)(a0); \ + la reg2, dest; \ +illegal ## testnum: \ + inst reg1, reg2; \ la a3, dest; \ vsd vx2, a3; \ fence; \ vtcode1 ## testnum: \ add x2, x2, x3; \ -illegal ## testnum: \ - inst reg1, reg2, reg3; \ stop; \ vtcode2 ## testnum: \ add x2, x2, x3; \ @@ -588,12 +590,13 @@ vtcode2 ## testnum: \ handler ## testnum: \ vxcptkill; \ li x28,2; \ - mfpcr a0,cr6; \ - li a1,26; \ - bne a0,a1,fail; \ - mfpcr a0,cr2; \ - la a1,illegal ## testnum; \ + vxcptcause a0; \ + li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \ bne a0,a1,fail; \ + vxcptaux a0; \ + la a1, illegal ## testnum; \ + lw a2, 0(a1); \ + bne a0, a2, fail; \ vsetcfg 32,0; \ li a0,4; \ vsetvl a0,a0; \ @@ -620,7 +623,8 @@ handler ## testnum: \ li x28,5; \ bne a1,a2,fail; \ -#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, aux) \ +#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ + setpcr status, SR_EI; \ la a0, handler ## testnum; \ mtpcr a0, evec; \ vsetcfg nxreg, nfreg; \ @@ -632,14 +636,13 @@ handler ## testnum: \ vld vx3, a1; \ lui a0,%hi(vtcode1 ## testnum); \ vf %lo(vtcode1 ## testnum)(a0); \ - la reg2, dest; \ -illegal ## testnum: \ - inst reg1, reg2; \ la a3, dest; \ vsd vx2, a3; \ fence; \ vtcode1 ## testnum: \ add x2, x2, x3; \ +illegal ## testnum: \ + inst reg1, reg2, reg3; \ stop; \ vtcode2 ## testnum: \ add x2, x2, x3; \ @@ -647,12 +650,12 @@ vtcode2 ## testnum: \ handler ## testnum: \ vxcptkill; \ li x28,2; \ - mfpcr a0,cr6; \ - li a1,27; \ + vxcptcause a0; \ + li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \ + bne a0,a1,fail; \ + vxcptaux a0; \ + la a1,illegal ## testnum; \ bne a0,a1,fail; \ - mfpcr a0, cr2; \ - li a1, aux; \ - bne a0, a1, fail; \ vsetcfg 32,0; \ li a0,4; \ vsetvl a0,a0; \ @@ -679,7 +682,6 @@ handler ## testnum: \ li x28,5; \ bne a1,a2,fail; \ - #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in x28) #----------------------------------------------------------------------- diff --git a/isa/rv64sv/Makefrag b/isa/rv64sv/Makefrag index b892000..9a2746c 100644 --- a/isa/rv64sv/Makefrag +++ b/isa/rv64sv/Makefrag @@ -3,9 +3,12 @@ #----------------------------------------------------------------------- rv64sv_sc_tests = \ - illegal_tvec_cmd illegal_tvec_regid \ + illegal_cfg_nxpr illegal_cfg_nfpr illegal_inst privileged_inst \ + illegal_tvec_regid \ illegal_vt_inst illegal_vt_regid \ ma_utld ma_utsd ma_vld ma_vsd \ ma_vt_inst \ rv64sv_p_tests = $(addprefix rv64sv-p-, $(rv64sv_sc_tests)) + +spike_tests += $(rv64sv_p_tests) diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S new file mode 100644 index 0000000..b271268 --- /dev/null +++ b/isa/rv64sv/illegal_cfg_nfpr.S @@ -0,0 +1,102 @@ +#***************************************************************************** +# illegal_tvec_cmd.S +#----------------------------------------------------------------------------- +# +# Test illegal tvec command trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + setpcr status, SR_EI # enable interrupt + + la a3,handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status + + li a0,33 + slli a0,a0,6 + vsetcfg a0 + +vtcode2: + add x2,x2,x3 + stop + +handler: + vxcptkill + + li x28,2 + + # check cause + vxcptcause a3 + li a4,HWACHA_CAUSE_ILLEGAL_CFG + bne a3,a4,fail + + # check vec irq aux + vxcptaux a3 + li a4, 1 + bne a3,a4,fail + + # make sure vector unit has cleared out + vsetcfg 32,0 + li a3,4 + vsetvl a3,a3 + + la a3,src1 + la a4,src2 + vld vx2,a3 + vld vx3,a4 + lui a0,%hi(vtcode2) + vf %lo(vtcode2)(a0) + la a5,dest + vsd vx2,a5 + fence + + ld a1,0(a5) + li a2,5 + li x28,2 + bne a1,a2,fail + ld a1,8(a5) + li x28,3 + bne a1,a2,fail + ld a1,16(a5) + li x28,4 + bne a1,a2,fail + ld a1,24(a5) + li x28,5 + bne a1,a2,fail + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +src1: + .dword 1 + .dword 2 + .dword 3 + .dword 4 +src2: + .dword 4 + .dword 3 + .dword 2 + .dword 1 +dest: + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + +RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S new file mode 100644 index 0000000..8dac90d --- /dev/null +++ b/isa/rv64sv/illegal_cfg_nxpr.S @@ -0,0 +1,101 @@ +#***************************************************************************** +# illegal_tvec_cmd.S +#----------------------------------------------------------------------------- +# +# Test illegal tvec command trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + setpcr status, SR_EI # enable interrupt + + la a3,handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status + + li a0,33 + vsetcfg a0 + +vtcode2: + add x2,x2,x3 + stop + +handler: + vxcptkill + + li x28,2 + + # check cause + vxcptcause a3 + li a4,HWACHA_CAUSE_ILLEGAL_CFG + bne a3,a4,fail + + # check vec irq aux + vxcptaux a3 + li a4, 0 + bne a3,a4,fail + + # make sure vector unit has cleared out + vsetcfg 32,0 + li a3,4 + vsetvl a3,a3 + + la a3,src1 + la a4,src2 + vld vx2,a3 + vld vx3,a4 + lui a0,%hi(vtcode2) + vf %lo(vtcode2)(a0) + la a5,dest + vsd vx2,a5 + fence + + ld a1,0(a5) + li a2,5 + li x28,2 + bne a1,a2,fail + ld a1,8(a5) + li x28,3 + bne a1,a2,fail + ld a1,16(a5) + li x28,4 + bne a1,a2,fail + ld a1,24(a5) + li x28,5 + bne a1,a2,fail + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +src1: + .dword 1 + .dword 2 + .dword 3 + .dword 4 +src2: + .dword 4 + .dword 3 + .dword 2 + .dword 1 +dest: + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + +RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_inst.S index 8943d86..cddae29 100644 --- a/isa/rv64sv/illegal_tvec_cmd.S +++ b/isa/rv64sv/illegal_inst.S @@ -11,28 +11,23 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status + + .word 0xff00002b vsetcfg 32,0 li a3,4 vsetvl a3,a3 - la a3, dest+1 - vmsv vx1, a3 - addi a3, x0, 0x1 - sll a3, a3, 12 - venqcmd a3, x0 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - fence - vtcode1: lw x2, 0(x1) stop @@ -47,14 +42,13 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,27 + vxcptcause a3 + li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 - addi a4, x0, 0x1 - sll a4, a4, 12 + vxcptaux a3 + li a4, 0xff00002b bne a3,a4,fail # make sure vector unit has cleared out diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S index 4f48f8f..d57aeca 100644 --- a/isa/rv64sv/illegal_tvec_regid.S +++ b/isa/rv64sv/illegal_tvec_regid.S @@ -11,17 +11,17 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a0,cr0 - li a1,1 - slli a2,a1,8 - or a0,a0,a1 # enable traps - mtpcr a0,cr0 + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status - TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2, 0x931c7) - TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2, 0x831c7) + TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2) + TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2) - TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2, 0x9b9e7) - TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2, 0x8b9e7) + TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2) + TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2) TEST_PASSFAIL diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S index d0e5574..de026f4 100644 --- a/isa/rv64sv/illegal_vt_inst.S +++ b/isa/rv64sv/illegal_vt_inst.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -48,12 +50,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,26 + vxcptcause a3 + li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION bne a3,a4,fail # check badvaddr - mfpcr a3,cr2 + vxcptaux a3 la a4,illegal bne a3,a4,fail diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S index 8baa918..e612a86 100644 --- a/isa/rv64sv/illegal_vt_regid.S +++ b/isa/rv64sv/illegal_vt_regid.S @@ -11,11 +11,11 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a0,cr0 - li a1,1 - slli a2,a1,8 - or a0,a0,a1 # enable traps - mtpcr a0,cr0 + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2) TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2) diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S index 7b5db04..2cc42bc 100644 --- a/isa/rv64sv/ma_utld.S +++ b/isa/rv64sv/ma_utld.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -44,12 +46,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,28 + vxcptcause a3 + li a4,HWACHA_CAUSE_MISALIGNED_LOAD bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 + vxcptaux a3 la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S index 3b9e094..ead6c2c 100644 --- a/isa/rv64sv/ma_utsd.S +++ b/isa/rv64sv/ma_utsd.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -46,12 +48,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,29 + vxcptcause a3 + li a4,HWACHA_CAUSE_MISALIGNED_STORE bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 + vxcptaux a3 la a4, dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S index bcf4b5a..3ea11e9 100644 --- a/isa/rv64sv/ma_vld.S +++ b/isa/rv64sv/ma_vld.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -45,12 +47,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,28 + vxcptcause a3 + li a4,HWACHA_CAUSE_MISALIGNED_LOAD bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 + vxcptaux a3 la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S index 6822250..fbbc0cd 100644 --- a/isa/rv64sv/ma_vsd.S +++ b/isa/rv64sv/ma_vsd.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -48,12 +50,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,29 + vxcptcause a3 + li a4,HWACHA_CAUSE_MISALIGNED_STORE bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 + vxcptaux a3 la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S index 185924c..d76f26c 100644 --- a/isa/rv64sv/ma_vt_inst.S +++ b/isa/rv64sv/ma_vt_inst.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -38,12 +40,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,24 + vxcptcause a3 + li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH bne a3,a4,fail # check badvaddr - mfpcr a3,cr2 + vxcptaux a3 la a4,vtcode1+2 bne a3,a4,fail diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S new file mode 100644 index 0000000..3f04f60 --- /dev/null +++ b/isa/rv64sv/privileged_inst.S @@ -0,0 +1,105 @@ +#***************************************************************************** +# illegal_tvec_cmd.S +#----------------------------------------------------------------------------- +# +# Test illegal tvec command trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + setpcr status, SR_EI # enable interrupt + + la a3,handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status + + setpcr status, SR_U64 + clearpcr status, SR_S # clear S bit + +privileged_inst: + vxcptcause a3 # privileged inst + +vtcode2: + add x2,x2,x3 + stop + +handler: + vxcptkill + + li x28,2 + + # check cause + vxcptcause a3 + li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION + bne a3,a4,fail + + # check vec irq aux + vxcptaux a3 + la a4, privileged_inst + lw a5, 0(a4) + bne a3,a5,fail + + # make sure vector unit has cleared out + vsetcfg 32,0 + li a3,4 + vsetvl a3,a3 + + la a3,src1 + la a4,src2 + vld vx2,a3 + vld vx3,a4 + lui a0,%hi(vtcode2) + vf %lo(vtcode2)(a0) + la a5,dest + vsd vx2,a5 + fence + + ld a1,0(a5) + li a2,5 + li x28,2 + bne a1,a2,fail + ld a1,8(a5) + li x28,3 + bne a1,a2,fail + ld a1,16(a5) + li x28,4 + bne a1,a2,fail + ld a1,24(a5) + li x28,5 + bne a1,a2,fail + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +src1: + .dword 1 + .dword 2 + .dword 3 + .dword 4 +src2: + .dword 4 + .dword 3 + .dword 2 + .dword 1 +dest: + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + .dword 0xdeadbeefcafebabe + +RVTEST_DATA_END |