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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-11 16:25:24 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-11 16:25:24 -0700 |
| commit | ee576c08929905b07692f2e4c8a6b032752ae102 (patch) | |
| tree | 8789ff5b0e09de9cded9907bfef9cb2348c58eb2 /isa/rv64si | |
| parent | 72d284b28c9b728fd978b5c17a1fefc1888623db (diff) | |
| download | riscv-tests-ee576c08929905b07692f2e4c8a6b032752ae102.zip riscv-tests-ee576c08929905b07692f2e4c8a6b032752ae102.tar.gz riscv-tests-ee576c08929905b07692f2e4c8a6b032752ae102.tar.bz2 | |
Revert "scall: make the intention of the test in machine mode more clear (#246)"
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c.
Resolves #256
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/scall.S | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index 77718f2..82f202a 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -19,6 +19,7 @@ RVTEST_CODE_BEGIN #define scause mcause #define sepc mepc #define sret mret + #define stvec_handler mtvec_handler #undef SSTATUS_SPP #define SSTATUS_SPP MSTATUS_MPP #endif @@ -56,11 +57,6 @@ do_scall: TEST_PASSFAIL -# make the linker not find the symbol stvec_handler when running in machine -# mode. env/p/riscv_test.h sets stvec to the address of that symbol in case it -# is non-zero. thus, effectively, we don't register a handler for scalls, so -# that the default handler (trap_vector) is used. -#ifndef __MACHINE_MODE .align 2 .global stvec_handler stvec_handler: @@ -70,7 +66,6 @@ stvec_handler: csrr t0, sepc bne t0, t2, fail j pass -#endif RVTEST_CODE_END |