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author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2020-11-11 17:09:15 +0800 |
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committer | GitHub <noreply@github.com> | 2020-11-11 01:09:15 -0800 |
commit | 5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5 (patch) | |
tree | 4a9483bc0b6fe2c770d8844534f89a88adbdce7d /isa/rv32uzfh/fclass.S | |
parent | c4217d88bce9f805a81f42e86ff56ed363931d69 (diff) | |
download | riscv-tests-5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5.zip riscv-tests-5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5.tar.gz riscv-tests-5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5.tar.bz2 |
add zfh (float16) test case and related macros (#301)
* ext: add zfh extension test case and related macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* build: add zfh to target
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'isa/rv32uzfh/fclass.S')
-rw-r--r-- | isa/rv32uzfh/fclass.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/isa/rv32uzfh/fclass.S b/isa/rv32uzfh/fclass.S new file mode 100644 index 0000000..b1fcf24 --- /dev/null +++ b/isa/rv32uzfh/fclass.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fclass.S" |