add zfh (float16) test case and related macros (#301)

* ext: add zfh extension test case and related macro

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* build: add zfh to target

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

12 files changed, 120 insertions, 0 deletions

diff --git a/isa/rv32uzfh/Makefrag b/isa/rv32uzfh/Makefrag
new file mode 100644
index 0000000..5d9869d
--- /dev/null
+++ b/isa/rv32uzfh/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32uzfh tests
+#-----------------------------------------------------------------------
+
+rv32uzfh_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move recoding \
+
+rv32uzfh_p_tests = $(addprefix rv32uzfh-p-, $(rv32uzfh_sc_tests))
+rv32uzfh_v_tests = $(addprefix rv32uzfh-v-, $(rv32uzfh_sc_tests))
+
+spike32_tests += $(rv32uzfh_p_tests) $(rv32uzfh_v_tests)
diff --git a/isa/rv32uzfh/fadd.S b/isa/rv32uzfh/fadd.S
new file mode 100644
index 0000000..11dba9d
--- /dev/null
+++ b/isa/rv32uzfh/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fadd.S"
diff --git a/isa/rv32uzfh/fclass.S b/isa/rv32uzfh/fclass.S
new file mode 100644
index 0000000..b1fcf24
--- /dev/null
+++ b/isa/rv32uzfh/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fclass.S"
diff --git a/isa/rv32uzfh/fcmp.S b/isa/rv32uzfh/fcmp.S
new file mode 100644
index 0000000..9793dea
--- /dev/null
+++ b/isa/rv32uzfh/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fcmp.S"
diff --git a/isa/rv32uzfh/fcvt.S b/isa/rv32uzfh/fcvt.S
new file mode 100644
index 0000000..2b5bf5a
--- /dev/null
+++ b/isa/rv32uzfh/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt.S"
diff --git a/isa/rv32uzfh/fcvt_w.S b/isa/rv32uzfh/fcvt_w.S
new file mode 100644
index 0000000..d532b35
--- /dev/null
+++ b/isa/rv32uzfh/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uzfh/fcvt_w.S"
diff --git a/isa/rv32uzfh/fdiv.S b/isa/rv32uzfh/fdiv.S
new file mode 100644
index 0000000..2bf43a7
--- /dev/null
+++ b/isa/rv32uzfh/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fdiv.S"
diff --git a/isa/rv32uzfh/fmadd.S b/isa/rv32uzfh/fmadd.S
new file mode 100644
index 0000000..2a5ea91
--- /dev/null
+++ b/isa/rv32uzfh/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmadd.S"
diff --git a/isa/rv32uzfh/fmin.S b/isa/rv32uzfh/fmin.S
new file mode 100644
index 0000000..360e02f
--- /dev/null
+++ b/isa/rv32uzfh/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/fmin.S"
diff --git a/isa/rv32uzfh/ldst.S b/isa/rv32uzfh/ldst.S
new file mode 100644
index 0000000..7f09872
--- /dev/null
+++ b/isa/rv32uzfh/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0xcafe4000, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); lw a0, 20(a1))
+  TEST_CASE(3, a0, 0xabadbf80, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); lw a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf80bf80
+.word 0x40004000
+.word 0x40404040
+.word 0xc080c080
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/isa/rv32uzfh/move.S b/isa/rv32uzfh/move.S
new file mode 100644
index 0000000..b399a76
--- /dev/null
+++ b/isa/rv32uzfh/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/move.S"
diff --git a/isa/rv32uzfh/recoding.S b/isa/rv32uzfh/recoding.S
new file mode 100644
index 0000000..271a5cb
--- /dev/null
+++ b/isa/rv32uzfh/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UH
+#define RVTEST_RV64UH RVTEST_RV32UH
+
+#include "../rv64uzfh/recoding.S"