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| author | Tim Newsome <tim@sifive.com> | 2018-12-31 13:10:29 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-12-31 13:10:29 -0800 |
| commit | a5d280990e7d258b76d2154c83ecae271511426c (patch) | |
| tree | 24e88349c5fdc807ffaf740a0957bccc5e8312c7 /debug/targets | |
| parent | d2b8b97afbc7317cc9d67cf360819935df1efef4 (diff) | |
| download | riscv-tests-a5d280990e7d258b76d2154c83ecae271511426c.zip riscv-tests-a5d280990e7d258b76d2154c83ecae271511426c.tar.gz riscv-tests-a5d280990e7d258b76d2154c83ecae271511426c.tar.bz2 | |
Add testing of run-test/idle cases.
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 3 |
6 files changed, 7 insertions, 6 deletions
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index c45013f..a2951c1 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -10,4 +10,4 @@ class spike32_2(targets.Target): implements_custom_test = True def create(self): - return testlib.Spike(self, progbufsize=0) + return testlib.Spike(self, progbufsize=0, dmi_rti=4) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 6c90b7c..8872ad3 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -10,4 +10,4 @@ class spike32_2(targets.Target): implements_custom_test = True def create(self): - return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0) + return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index a831ecb..e633eea 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -17,4 +17,4 @@ class spike32(targets.Target): def create(self): # 64-bit FPRs on 32-bit target - return testlib.Spike(self, isa="RV32IMAFDC") + return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4) diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 9cb3a44..1da7116 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -10,4 +10,4 @@ class spike64_2_rtos(targets.Target): implements_custom_test = True def create(self): - return testlib.Spike(self) + return testlib.Spike(self, abstract_rti=30) diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 23ae06b..e981105 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -10,4 +10,4 @@ class spike64_2(targets.Target): implements_custom_test = True def create(self): - return testlib.Spike(self, isa="RV64IMAFD") + return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index d0eaf5c..fdb1282 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -17,4 +17,5 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only - return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0) + return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0, + abstract_rti=30) |