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| author | Tim Newsome <tim@sifive.com> | 2017-10-05 12:48:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-05 12:48:40 -0700 |
| commit | cad03ed0e58693257176ebaf4cbb70484a44fd2e (patch) | |
| tree | cdd02426a6a429c2ac5ebf4d781b3519ea0c63f4 /debug/targets/RISC-V/spike64.py | |
| parent | 5eb2cf39af91f9d886e28175b729f02684c27df4 (diff) | |
| parent | 9091137e4a4797a91179ab73886697c7fe270da2 (diff) | |
| download | riscv-tests-interrupts.zip riscv-tests-interrupts.tar.gz riscv-tests-interrupts.tar.bz2 | |
Merge branch 'master' into interruptsinterrupts
Diffstat (limited to 'debug/targets/RISC-V/spike64.py')
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 6e3da89..2cd67a5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -6,12 +6,12 @@ class spike64_hart(targets.Hart): ram = 0x1212340000 ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 - reset_vector = 0x1000 + reset_vectors = [0x1000] link_script_path = "spike64.lds" class spike64(targets.Target): harts = [spike64_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-1.cfg" timeout_sec = 30 def create(self): |