diff options
author | Tim Newsome <tim@sifive.com> | 2017-10-05 12:48:40 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2017-10-05 12:48:40 -0700 |
commit | cad03ed0e58693257176ebaf4cbb70484a44fd2e (patch) | |
tree | cdd02426a6a429c2ac5ebf4d781b3519ea0c63f4 /debug/targets/RISC-V | |
parent | 5eb2cf39af91f9d886e28175b729f02684c27df4 (diff) | |
parent | 9091137e4a4797a91179ab73886697c7fe270da2 (diff) | |
download | riscv-tests-interrupts.zip riscv-tests-interrupts.tar.gz riscv-tests-interrupts.tar.bz2 |
Merge branch 'master' into interruptsinterrupts
Diffstat (limited to 'debug/targets/RISC-V')
-rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 16 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 19 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg (renamed from debug/targets/RISC-V/spike.cfg) | 1 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 12 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32.py | 4 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 12 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 2 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64.py | 4 |
9 files changed, 66 insertions, 6 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg new file mode 100644 index 0000000..fc20b53 --- /dev/null +++ b/debug/targets/RISC-V/spike-1.cfg @@ -0,0 +1,16 @@ +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable + +init +reset halt diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg new file mode 100644 index 0000000..17526ec --- /dev/null +++ b/debug/targets/RISC-V/spike-2.cfg @@ -0,0 +1,19 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME_0 $_CHIPNAME.cpu0 +set _TARGETNAME_1 $_CHIPNAME.cpu1 +target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 +target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 + +gdb_report_data_abort enable + +init +reset halt diff --git a/debug/targets/RISC-V/spike.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 9b1841c..799e3cb 100644 --- a/debug/targets/RISC-V/spike.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -1,3 +1,4 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. adapter_khz 10000 interface remote_bitbang diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py new file mode 100644 index 0000000..a7b9a1c --- /dev/null +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -0,0 +1,12 @@ +import targets +import testlib + +import spike32 # pylint: disable=import-error + +class spike32_2(targets.Target): + harts = [spike32.spike32_hart(), spike32.spike32_hart()] + openocd_config_path = "spike-rtos.cfg" + timeout_sec = 30 + + def create(self): + return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 6cf558d..719009d 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -5,7 +5,7 @@ import spike32 # pylint: disable=import-error class spike32_2(targets.Target): harts = [spike32.spike32_hart(), spike32.spike32_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-2.cfg" timeout_sec = 30 def create(self): diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 665d7e9..809463c 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -6,12 +6,12 @@ class spike32_hart(targets.Hart): ram = 0x10000000 ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 - reset_vector = 0x1000 + reset_vectors = [0x1000] link_script_path = "spike32.lds" class spike32(targets.Target): harts = [spike32_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-1.cfg" timeout_sec = 30 def create(self): diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py new file mode 100644 index 0000000..d65d2ab --- /dev/null +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -0,0 +1,12 @@ +import targets +import testlib + +import spike64 # pylint: disable=import-error + +class spike64_2_rtos(targets.Target): + harts = [spike64.spike64_hart(), spike64.spike64_hart()] + openocd_config_path = "spike-rtos.cfg" + timeout_sec = 30 + + def create(self): + return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index c6321dc..709ebbe 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -5,7 +5,7 @@ import spike64 # pylint: disable=import-error class spike64_2(targets.Target): harts = [spike64.spike64_hart(), spike64.spike64_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-2.cfg" timeout_sec = 30 def create(self): diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 6e3da89..2cd67a5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -6,12 +6,12 @@ class spike64_hart(targets.Hart): ram = 0x1212340000 ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 - reset_vector = 0x1000 + reset_vectors = [0x1000] link_script_path = "spike64.lds" class spike64(targets.Target): harts = [spike64_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-1.cfg" timeout_sec = 30 def create(self): |