| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-04-30 | support emulation of misaligned vector loads/stores | Andrew Waterman | 1 | -0/+14 | |
| 2024-04-30 | Support emulation of misaligned FLH/FSH | Andrew Waterman | 1 | -1/+8 | |
| 2024-04-25 | Fix emulation of misaligned c.swsp/c.sdsp with rd=x0 | Andrew Waterman | 1 | -2/+2 | |
| 2021-05-05 | machine: replace `mbadaddr` with `mtval` (#242) | Saleem Abdulrasool | 1 | -2/+2 | |
| The LLVM IAS does not support the older name for the `mtval` CSR. This updates the name to the current spelling, which is required to build with the LLVM IAS. This remains compatible with binutils as well. | |||||
| 2020-11-23 | Fix emulation of misaligned access on big endian target (#224) | Marcus Comstedt | 1 | -2/+12 | |
| 2018-12-02 | Delegate misaligned AMOs as access exceptions, not misaligned | Andrew Waterman | 1 | -2/+8 | |
| This indicates the access is actually invalid, i.e., should not be emulated. | |||||
| 2018-07-09 | Properly license all nontrivial files | Andrew Waterman | 1 | -0/+2 | |
| 2017-07-17 | Fix emulation of misaligned RVC loads/stores | Andrew Waterman | 1 | -2/+5 | |
| We were accidentally advancing the PC by 4, not 2. | |||||
| 2017-02-15 | Emulate RVFC instructions | Andrew Waterman | 1 | -0/+49 | |
| 2016-12-06 | avoid non-standard predefined macros | Andrew Waterman | 1 | -2/+2 | |
| 2016-07-19 | Handle misaligned loads in ascending order of byte address | Andrew Waterman | 1 | -1/+1 | |
| 2016-04-29 | Use mbadaddr to speed up misaligned ld/st emulation | Andrew Waterman | 1 | -2/+2 | |
| 2016-03-09 | Factor emulation routines into multiple files | Andrew Waterman | 1 | -0/+85 | |
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index : rocket-tools/riscv-pk.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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