From ce0312a91258aaf6e26e95c90394e45cb9ff4096 Mon Sep 17 00:00:00 2001 From: brs Date: Thu, 19 Oct 2023 10:45:27 -0500 Subject: Making explicit that the aq bit is set for load-acquire, rl bit is set for store-releasee --- unratified/rv_zalasr | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/unratified/rv_zalasr b/unratified/rv_zalasr index 84dbe52..43af470 100644 --- a/unratified/rv_zalasr +++ b/unratified/rv_zalasr @@ -1,8 +1,8 @@ -lb.aq rd rs1 rl 31..27=6 24..20=0 14..12=0 6..2=0x0B 1..0=3 -lh.aq rd rs1 rl 31..27=6 24..20=0 14..12=1 6..2=0x0B 1..0=3 -lw.aq rd rs1 rl 31..27=6 24..20=0 14..12=2 6..2=0x0B 1..0=3 -ld.aq rd rs1 rl 31..27=6 24..20=0 14..12=3 6..2=0x0B 1..0=3 -sb.rl rs1 rs2 aq 31..27=7 14..12=0 11..7=0 6..2=0x0B 1..0=3 -sh.rl rs1 rs2 aq 31..27=7 14..12=1 11..7=0 6..2=0x0B 1..0=3 -sw.rl rs1 rs2 aq 31..27=7 14..12=2 11..7=0 6..2=0x0B 1..0=3 -sd.rl rs1 rs2 aq 31..27=7 14..12=3 11..7=0 6..2=0x0B 1..0=3 +lb.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=0 6..2=0x0B 1..0=3 +lh.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=1 6..2=0x0B 1..0=3 +lw.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=2 6..2=0x0B 1..0=3 +ld.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=3 6..2=0x0B 1..0=3 +sb.rl rs1 rs2 aq 25=1 31..27=7 14..12=0 11..7=0 6..2=0x0B 1..0=3 +sh.rl rs1 rs2 aq 25=1 31..27=7 14..12=1 11..7=0 6..2=0x0B 1..0=3 +sw.rl rs1 rs2 aq 25=1 31..27=7 14..12=2 11..7=0 6..2=0x0B 1..0=3 +sd.rl rs1 rs2 aq 25=1 31..27=7 14..12=3 11..7=0 6..2=0x0B 1..0=3 -- cgit v1.1