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rocket-tools/riscv-isa-sim.git
confprec
cs250
csr-init-fixes
cycleh
debug_rom
debug_rom_fence
device_flags
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dts_parsing
dynamic
eos18-bringup
factor-out-macros
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fp-encoding
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hwachav4
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itrigger-etrigger-cleanup
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nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
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rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
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tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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path:
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/
riscv
/
insns
/
xori.h
blob: 33ce6307419d25055922e60bf4da30c89e3de8b3 (
plain
)
1
WRITE_RD
(
insn
.
i_imm
() ^
RS1
);
