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rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
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eos18-bringup
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path:
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/
riscv
/
insns
/
sraw.h
blob: 111f6328aeff8b4d4911796246ec7278bc69f9bb (
plain
)
1
RDR
=
sext32
(
sreg_t
(
RS2
) >> (
RS1
&
0x1F
));
