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rocket-tools/riscv-isa-sim.git
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path:
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/
riscv
/
insns
/
sllw.h
blob: 521c0f7e5eb8b8f3f03adabd23fa2fce4fbff19d (
plain
)
1
RDR
=
sext32
(
RS1
<< (
RS2
&
0x1F
));
