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rocket-tools/riscv-isa-sim.git
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path:
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/
riscv
/
insns
/
lw_aq.h
blob: 88917b5183c6d7e202b4ab4275035b8564058cda (
plain
)
1
2
require_extension
(
EXT_ZALASR
);
WRITE_RD
(
MMU
.
load
<
int32_t
>(
RS1
));