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rocket-tools/riscv-isa-sim.git
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path:
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/
riscv
/
insns
/
c_lw.h
blob: 63b708c9ad3d3b19aa587ff40dc07ca7ee498229 (
plain
)
1
2
require_extension
(
EXT_ZCA
);
WRITE_RVC_RS2S
(
MMU
.
load
<
int32_t
>(
RVC_RS1S
+
insn
.
rvc_lw_imm
()));