index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speed2
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
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author
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Mode
Name
Size
d---------
.github
/
workflows
36
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plain
-rw-r--r--
.gitignore
57
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-rw-r--r--
ChangeLog.md
966
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-rw-r--r--
LICENSE
1403
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-rw-r--r--
Makefile.in
17163
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-rw-r--r--
README.md
7886
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-rw-r--r--
VERSION
34
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-rw-r--r--
aclocal.m4
10832
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plain
d---------
arch_test_target
/
spike
32
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plain
-rw-r--r--
ax_append_flag.m4
1552
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plain
-rw-r--r--
ax_append_link_flags.m4
1711
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-rw-r--r--
ax_check_link_flag.m4
1956
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-rw-r--r--
ax_require_defined.m4
1218
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d---------
ci-tests
38
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-rw-r--r--
config.h.in
3203
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-rwxr-xr-x
configure
186610
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plain
-rw-r--r--
configure.ac
4874
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plain
d---------
customext
206
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plain
d---------
debug_rom
187
log
plain
d---------
disasm
153
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plain
d---------
fdt
573
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plain
d---------
fesvr
1276
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plain
-rw-r--r--
riscv-disasm.pc.in
283
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plain
-rw-r--r--
riscv-fesvr.pc.in
284
log
plain
d---------
riscv
1909
log
plain
d---------
scripts
204
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d---------
softfloat
10213
log
plain
d---------
spike_dasm
181
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plain
d---------
spike_main
250
log
plain
d---------
tests
111
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plain