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2022-11-15update module_tYenHaoChen2-31/+82
2022-11-15add itrigger_t and etrigger_tYenHaoChen2-1/+153
2022-11-15update debug_defines.hYenHaoChen1-892/+1432
2022-11-15add disabled_trigger_t to triggersYenHaoChen2-0/+27
2022-11-15trigger_t: Protect destructor and memory_access_match()Tim Newsome1-7/+3
2022-11-15triggers: Move trigger_t.hit to mcontrol_t.hitTim Newsome1-2/+1
2022-11-15triggers: Access action bit through get_action()Tim Newsome2-2/+4
2022-11-15triggers: rename chainTim Newsome2-8/+8
2022-11-15triggers: Rename/move dmodeTim Newsome2-5/+7
2022-11-15triggers: rename storeTim Newsome3-7/+7
2022-11-15Triggers: rename loadTim Newsome3-7/+7
2022-11-15Triggers rename executeTim Newsome3-8/+8
2022-11-15Move tdata2 from mcontrol_t into its own class.YenHaoChen2-16/+22
2022-10-20Merge pull request #1122 from riscv-software-src/more-mmu-simplificationAndrew Waterman70-218/+189
2022-10-20Use reg_t, not uint64_t, for address-like quantitiesAndrew Waterman1-2/+2
2022-10-20Fix tval reporting for CBOsAndrew Waterman1-2/+1
2022-10-20move fucntion cto() from processor.h to arith.hYenHaoChen3-9/+10
2022-10-19Template-ize storesAndrew Waterman17-40/+30
2022-10-19Template-ize loadsAndrew Waterman21-53/+37
2022-10-19Template-ize AMOsAndrew Waterman20-34/+29
2022-10-19DRY in store-conditional instructionsAndrew Waterman3-12/+15
2022-10-19Simplify check_load_reservationAndrew Waterman1-2/+2
2022-10-19Template-ize hypervisor loads and storesAndrew Waterman14-33/+28
2022-10-19Remove require_alignment flag from loadsAndrew Waterman2-7/+7
2022-10-19Fix imprecise exception on LR to MMIO spaceAndrew Waterman4-17/+14
2022-10-19Template-ize load_func macroAndrew Waterman1-15/+20
2022-10-19Template-ize store_func macroAndrew Waterman1-14/+18
2022-10-19No need to require_alignment for the load part of the AMOAndrew Waterman1-1/+1
2022-10-19Remove actually_store and require_alignment parameters from store_func macroAndrew Waterman1-8/+6
2022-10-19do memcpy only for actually_store in store_slow_path_intrapageWeiwei Li1-2/+4
2022-10-19Fix missing sentinel warning in dts.cc when using gnu++17 standardWeiwei Li1-1/+1
2022-10-17fix clang buildAndrew Waterman1-1/+1
2022-10-17Add command to display privilege level in interactive modeJerry Zhao4-0/+32
2022-10-17Make PLIC/NS16550 coding style more conformantAndrew Waterman3-84/+61
2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman198-6885/+7749
2022-10-16Add interactive mode commands to read clint mtime/mtimecmpJerry Zhao3-0/+27
2022-10-14Add dump memory command to interactive modeJerry Zhao4-0/+29
2022-10-14Support command-line configuration of number of pmpregionsJerry Zhao4-2/+7
2022-10-14Merge pull request #1114 from riscv-software-src/data_optionalScott Johnson4-21/+21
2022-10-14In triggers, use optional<data> instead of {has_data, data}Andrew Waterman4-16/+17
2022-10-14Report error if an unsupported memory configuration is detectedParshintsev Anatoly1-6/+10
2022-10-13Remove unused field matched_t::dataAndrew Waterman2-5/+4
2022-10-13Merge pull request #1107 from riscv-software-src/simplify-ld-stAndrew Waterman3-179/+123
2022-10-11Set tval on illegal subforms of aes64ks1iAndrew Waterman1-4/+1
2022-10-07Add --dm-no-abstract-fpr option.Tim Newsome2-1/+2
2022-10-06Don't use reexecution as the means to implement trigger-afterAndrew Waterman3-10/+7
2022-10-06Fix endianness bug in fetch triggersAndrew Waterman1-2/+1
2022-10-06DRY in checking triggersAndrew Waterman2-42/+28
2022-10-06Move uncommon-case fetch functionality into fetch_slow_pathAndrew Waterman2-25/+25
2022-10-06Move all uncommon-case store functionality into store_slow_pathAndrew Waterman2-65/+46
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