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Debug mode (D-mode) can be considered an additional privilege mode.
This commit proposes printing D(-mode) instead of M(-mode) for D-mode.
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Print cache stats even when no access
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Allow client to override default names of caches
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Add cache statistics print on demand
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Spec says:
> This trigger matches on every instruction completed or trap
> taken from a privilege mode where the trigger is enabled.
Other (synchronous) traps were already correctly decrementing count,
but external interrupts (i.e. timer interrupts) were not.
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According to table in debug spec.
This has no visible effect, because every time we instantiate an
icount_t (in triggers::module_t::tdata1_write) we immediately call
tdata1_write() which sets these values, but it's cleaner this way.
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In multi-processor systems it is desired to track
caches separately by assigning unique names to them.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
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The cache stats are printed regardless on accesses they
recorded. This allows better insight into system operation
and provides consistent output for scripting.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
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With this change it is not necessary to wait for
tracer destructor to trigger statistics printout.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
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This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
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Commit 191634d285 changed the default kernel boot args from
"console=hvc0 earlycon=sbi" to "console=ttyS0 earlycon", but didn't
updated the spike usage help() function.
This commit introduces a new macro DEFAULT_KERNEL_BOOTARGS in order to
have a single definition. This macro is used everywhere in dts.cc and
spike.cc help() function.
Signed-off-by: Julien Olivain <ju.o@free.fr>
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Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
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* Move most ctrl-c logic to interactive()
* 5f4cabc was only a partial fix. This change catches more corner cases where the ctrlc is registered
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
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We don't model any sources of RNMI, so this is mostly vestigial.
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I believe the fact that mmu_t::refill_tlb was ignoring debug mode
was benign, but certainly paying attention to debug mode is OK.
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In keeping with the spirit of simif_t.
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In keeping with the spirit of simif_t.
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So we can soon convert those classes to use simif_t instead of sim_t.
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To be explicit about which methods of simif_t and htif_t we implement.
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Break out of the interactive_run->interactive_run loop when ctrlc_pressed
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
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Don't issue misaligned or non-power-of-2 MMIO accesses
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@aswaterman explains:
Rather than requiring each MMIO device to support arbitrary sizes and
alignments, decompose MMIO misaligned loads and stores in such a way
as to guarantee their constituent parts are always aligned.
(Specifically, they now always decompose to a sequence of one-byte
accesses.)
This is not a semantic change for main-memory accesses, but it is a
semantic change for I/O devices. It makes them more realistic, in that
most bus standards don't support non-power-of-2-sized accesses.
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Misaligned MMIO is unspecified but this is simple enough.
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update support for Zc* to v1.0.3
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Initialize MTIP at reset
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Define sim_t::INTERLEAVE so that it can be accessed by reference
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Since mtime and mtimecmp both initialize to 0, and "a machine timer
interrupt becomes pending whenever mtime contains a value greater than
or equal to mtimecmp," MTIP should be 1.
Before this change, MTIP would be 0 until the first increment, or
until reading/writing from CLINT regs (since clint_t::load() and
clint_t::store() call increment(0)).
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std::min takes its arguments by reference, so the arguments need to be
defined. An alternative would have been to force the problematic argument
into being an rvalue (e.g., by adding 0), but this approach seems to me
to be more robust.
This fixes compilation under -O0; see https://github.com/riscv-software-src/riscv-isa-sim/pull/1264#issuecomment-1451114717
@scottj97 I posit that this situation is unusual enough that it shouldn't
motivate us to test -O0 in CI.
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This is a large delta because the old implementation baked in multiple
assumptions about the contiguity of hart IDs.
As a side effect, fix implementation for big-endian hosts.
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It's safe to overwrite bytes when returning false.
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This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
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