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rocket-tools/riscv-isa-sim.git
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dynamic
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sifive/rvv0.9-phase2
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riscv
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plic.cc
Age
Commit message (
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Author
Files
Lines
2023-12-11
riscv: sim.cc: Parse for "sifive,plic-1.0.0" if "riscv,plic0" is absent
Tan En De
1
-1
/
+2
2023-12-08
Fix Spike --device option to pass on args to downstream plugins
joey0320
1
-1
/
+1
2023-06-20
device_t: Add device_factory_t's for ns16550/clint/plic
Jerry Zhao
1
-0
/
+37
2023-06-20
devices: Pass const pointers to sim_t to clint/plic
Jerry Zhao
1
-1
/
+1
2023-04-07
Implement pending bits for plic
Jiajie Chen
1
-1
/
+21
2023-03-09
Use simif_t instead of sim_t for clint/plic
Scott Johnson
1
-2
/
+2
2023-03-01
Fix PLIC on big-endian hosts
Andrew Waterman
1
-3
/
+3
2023-03-01
Remove unnecessary conditional in plic_t::load
Andrew Waterman
1
-3
/
+1
2023-03-01
Correctly instantiate PLIC contexts for mixed-hart targets
Andrew Waterman
1
-5
/
+8
2023-03-01
Refactor plic_t and plic_context_t initialization
Andrew Waterman
1
-18
/
+5
2023-02-28
Remove unused plic_context_t::num field
Andrew Waterman
1
-1
/
+0
2023-02-28
Remove unused plic_t::procs field
Andrew Waterman
1
-1
/
+1
2023-02-22
optimize `num_ids_word` init logic;
Wade
1
-6
/
+3
2023-02-18
fix unintentionally plic context update when `val > max_prio` and `offset == ...
Wade
1
-3
/
+4
2022-11-23
Make reserved PLIC behavior more realistic
Andrew Waterman
1
-22
/
+32
2022-10-17
Make PLIC/NS16550 coding style more conformant
Andrew Waterman
1
-73
/
+55
2022-04-20
Add PLIC emulation
Anup Patel
1
-0
/
+393