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rocket-tools/riscv-isa-sim.git
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mmu.h
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2024-01-24
Use designated initiallizers to construct xlate_flags_t objects
rbuchner
1
-27
/
+15
2023-08-27
report right pseudo-inst for guest PF caused for VS-stage addr trans
Ved Shanbhogue
1
-1
/
+1
2023-07-19
Merge pull request #1413 from YenHaoChen/pr-mcontrol-cbo-zero-tval
Andrew Waterman
1
-2
/
+10
2023-07-19
mcontrol/mcontrol6 triggers on cbo.flush/clean
YenHaoChen
1
-0
/
+3
2023-07-18
mmu: fetch instruction bytes in ascending order
Yinan Xu
1
-3
/
+3
2023-07-13
fix mcontrol's tval on cbo_zero
YenHaoChen
1
-1
/
+3
2023-07-13
refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameter
YenHaoChen
1
-1
/
+4
2023-06-19
Implement Zacas extension.
Gianluca Guida
1
-0
/
+11
2023-06-12
Fix PMP checking region of cache-block management instructions
YenHaoChen
1
-1
/
+1
2023-05-11
Plumb in effective virtual bit to take_trigger_action()
rbuchner
1
-1
/
+1
2023-05-11
Add split_misaligned_access() to mem_access_info_t
rbuchner
1
-0
/
+4
2023-05-11
Pass mem_access_info_t into walk()
rbuchner
1
-1
/
+1
2023-05-11
Adjust store_slow_path_intrapage to recieve a mem_access_info_t as input
Ryan Buchner
1
-1
/
+1
2023-05-11
Adjust load_slow_path_intrapage to recieve a mem_access_info_t as input
Ryan Buchner
1
-1
/
+1
2023-05-11
Add structure (mem_access_info_t) for holding memory access information
Ryan Buchner
1
-3
/
+31
2023-05-11
Add is_special_access() to xlate_flags_t
rbuchner
1
-2
/
+6
2023-05-11
Add xlate_flags_t struct
rbuchner
1
-21
/
+35
2023-05-11
Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRT
Ryan Buchner
1
-4
/
+4
2023-03-20
Implement Smrnmi extension
Andrew Waterman
1
-0
/
+1
2023-03-16
Make MPRV logic consistent; factor it out
Andrew Waterman
1
-0
/
+7
2023-03-04
Don't issue misaligned or non-power-of-2 MMIO accesses
Scott Johnson
1
-0
/
+1
2023-02-20
Rename host_pte_paddr to host_pte_addr
Scott Johnson
1
-6
/
+6
2023-02-04
Use relative path for fesvr/byteorder.h in mmu.h
Jerry Zhao
1
-1
/
+1
2023-01-27
Remove dirty_enabled from cfg_t
Aaron Durbin
1
-2
/
+0
2023-01-04
Respect --mmu-dirty flag instead of --enable-dirty
Jerry Zhao
1
-8
/
+1
2023-01-03
Respect --[no-]misaligned command-line flag
Andrew Waterman
1
-11
/
+7
2023-01-03
Merge pull request #1200 from riscv-software-src/mmio_pte
Andrew Waterman
1
-0
/
+49
2023-01-03
Support pte load/store from mmio regions
Jerry Zhao
1
-2
/
+2
2023-01-03
Pull pte load/store into methods of mmu_t
Jerry Zhao
1
-0
/
+49
2023-01-03
Add method to probe which memory regions are reservable
Jerry Zhao
1
-3
/
+3
2023-01-03
Specify addresses are physical for simif_t member functions
Jerry Zhao
1
-4
/
+4
2022-12-23
Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accesses
Jerry Zhao
1
-0
/
+1
2022-12-20
Replace compile-time conditional with run-time conditional for load/store log...
Jerry Zhao
1
-19
/
+4
2022-12-15
Rename memif_endianness_t to endianness_t
Jerry Zhao
1
-1
/
+1
2022-12-15
Pull memif_endianness_t into cfg.h
Jerry Zhao
1
-0
/
+1
2022-11-28
Restore fetch_jump_table to instruction fetch
Weiwei Li
1
-3
/
+2
2022-11-17
add support for zcmt
Weiwei Li
1
-0
/
+7
2022-10-25
Remove set_target_endianness | add --big-endian flag
Jerry Zhao
1
-10
/
+1
2022-10-20
Merge pull request #1122 from riscv-software-src/more-mmu-simplification
Andrew Waterman
1
-101
/
+82
2022-10-20
Use reg_t, not uint64_t, for address-like quantities
Andrew Waterman
1
-2
/
+2
2022-10-20
Fix tval reporting for CBOs
Andrew Waterman
1
-2
/
+1
2022-10-19
Template-ize stores
Andrew Waterman
1
-13
/
+3
2022-10-19
Template-ize loads
Andrew Waterman
1
-17
/
+1
2022-10-19
Template-ize AMOs
Andrew Waterman
1
-14
/
+9
2022-10-19
DRY in store-conditional instructions
Andrew Waterman
1
-0
/
+13
2022-10-19
Simplify check_load_reservation
Andrew Waterman
1
-2
/
+2
2022-10-19
Template-ize hypervisor loads and stores
Andrew Waterman
1
-20
/
+15
2022-10-19
Remove require_alignment flag from loads
Andrew Waterman
1
-5
/
+5
2022-10-19
Fix imprecise exception on LR to MMIO space
Andrew Waterman
1
-10
/
+7
2022-10-19
Template-ize load_func macro
Andrew Waterman
1
-15
/
+20
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