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2023-04-14Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li4-4/+4
2023-04-14Add support for new instructions of Zvfbfwma extensionWeiwei Li2-0/+10
2023-04-14Add support for new instructions of Zvfbfmin extensionWeiwei Li2-0/+10
2023-04-14Add support for new instructions of Zfbfmin extensionWeiwei Li2-0/+11
2023-04-03Implement Zfa.Philipp Tomsich33-0/+420
This passes our developer test suite, when comparing output (signature) against the SAIL implementation. If any corner-cases require additional changes after ACT goes upstream, we can apply an add-on patch.
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+15
We don't model any sources of RNMI, so this is mostly vestigial.
2023-02-21Remove redundant RVE related check in cm.mva01s and cm.mvsa01Weiwei Li2-6/+0
r1s/r2s > 16 when r1sc/r1sc >2. This will also trigger illegal instruction exception by CHECK_REG if RVE is enabled
2023-02-21Add r1s != r2s check for cm.mvsa01Weiwei Li1-0/+1
2023-02-21Update fields name for sreg1/sreg2Weiwei Li2-6/+6
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich2-0/+4
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
2022-12-05Merge pull request #1162 from riscv-software-src/sfenceAndrew Waterman2-3/+2
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode
2022-12-05SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modesAndrew Waterman1-0/+1
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213
2022-12-05Simplify implementation of SFENCE.W.INVALAndrew Waterman1-3/+1
For Spike, this instruction merely performs exception checks, just like SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR.
2022-11-28Merge pull request #1156 from plctlab/plct-zce-fixAndrew Waterman1-1/+1
Fix support for Zc*
2022-11-28Fix field extract for jvt.baseWeiwei Li1-1/+1
2022-11-21When resuming from debug mode, clear mstatus.MPRV if the new privilege mode ↵YenHaoChen1-0/+2
is less than M-mode (#1149)
2022-11-17add support for zcmtWeiwei Li1-0/+23
add suport for jvt: Table entries follow the current data endianness
2022-11-17add support for zcmpWeiwei Li6-0/+50
2022-11-17add support for zcbWeiwei Li12-0/+30
2022-11-17add support for zca zcd and zcfWeiwei Li35-43/+39
2022-10-25Change remaining vector FP16 instructions to require ZvfhAndrew Waterman15-44/+44
...as opposed to Zfh.
2022-10-25Change SEW=16 vfncvt.f.f.w and vfwcvt.f.f.v to require ZvfhminAndrew Waterman2-12/+12
...as opposed to Zfh.
2022-10-19Template-ize storesAndrew Waterman13-15/+15
2022-10-19Template-ize loadsAndrew Waterman16-18/+18
2022-10-19Template-ize AMOsAndrew Waterman18-18/+18
2022-10-19DRY in store-conditional instructionsAndrew Waterman2-12/+2
2022-10-19Template-ize hypervisor loads and storesAndrew Waterman13-13/+13
2022-10-19Fix imprecise exception on LR to MMIO spaceAndrew Waterman2-6/+2
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise.
2022-10-11Set tval on illegal subforms of aes64ks1iAndrew Waterman1-4/+1
h/t @YenHaoChen
2022-10-04Fix unused-variable warnings in P-extension instruction definitionsAndrew Waterman1-1/+0
2022-10-04Suppress unused-variable warnings in vector instruction definitionsAndrew Waterman6-10/+0
2022-10-04Suppress unused-variable warnings in AES codeAndrew Waterman1-2/+2
2022-10-04Suppress most unused variable warningsAndrew Waterman2-2/+2
2022-09-28Fix vmv.x.s for RV32Andrew Waterman1-8/+9
The Spike internals require that, when XLEN is narrower than reg_t, values be sign-extended to the width of reg_t.
2022-09-08Remove unnecessary argument alu(always false) from macroWeiwei Li3-3/+3
require_vector_novtype
2022-09-06fix comment in definition of vmv<nf>r.vAndrew Waterman1-1/+1
2022-09-06vmv<nf>r.v depends on vtype, and therefore should check villAndrew Waterman1-1/+1
2022-08-22Fix redundant loops when calculating vrgather.vi. (#1072)yangcheng1-6/+0
2022-08-12Remove unused code in vsmul* (#1069)ksco2-19/+2
2022-08-10Add space between if/while/switch and '('Weiwei Li47-56/+56
Add space between ')' and '{'
2022-08-04Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵liweiwei87-193/+193
instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com>
2022-08-01WFI condition fixCanberk Topal1-1/+3
Before this commit Spike was requiring S mode privilege even without S mode implemented. This commit fixes it. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2022-07-28Fix overflow issue of p-ext multiply instructions (#1053)ChunPing Chung8-8/+8
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome2-2/+16
Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode.
2022-04-10Adjust the access index of vs2 to zero in vmv_x_s.h (#969)Brandon Wu1-21/+17
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman7-7/+7
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write.
2022-03-29Fix start byte for vmv<nf>r.v (#959)liweiwei901-3/+4
'The instructions operate as if EEW=SEW.EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte should take sew into acount when vstart != 0
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-2/+2
This is a minor change, turning processor_t from a child class of isa_parser_t into a class that contains an isa_parser_t as a field. The point is that it is a step toward separating out "configuration" (and ISA string parsing) from processor state. This should be helpful for rejigging things so that we construct more from a supplied device tree.
2022-02-27perform hstatus probe/update for sret only when H extension enabled. (#934)Neel Gala1-5/+6
* perform hstatus probe/update for sret only when H extension enabled. * added missing parenthesis
2022-02-23csr: hyper: fix mstatus.mpp after mretChih-Min Chao1-1/+1
By spec 3.1.6.1 (original behavior) "x PP is set to the least-privileged supported mode (U if U-mode is implemented, else M)" By spec 8.6.4 (h-extension) "MRET first determines what the new privilege mode will be according to the values of MPP and MPV in mstatus or mstatush, as encoded in Table 8.8. MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-09-11 22:09:55 +0000