Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2023-04-14 | Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensions | Weiwei Li | 4 | -4/+4 | |
2023-04-14 | Add support for new instructions of Zvfbfwma extension | Weiwei Li | 2 | -0/+10 | |
2023-04-14 | Add support for new instructions of Zvfbfmin extension | Weiwei Li | 2 | -0/+10 | |
2023-04-14 | Add support for new instructions of Zfbfmin extension | Weiwei Li | 2 | -0/+11 | |
2023-04-03 | Implement Zfa. | Philipp Tomsich | 33 | -0/+420 | |
This passes our developer test suite, when comparing output (signature) against the SAIL implementation. If any corner-cases require additional changes after ACT goes upstream, we can apply an add-on patch. | |||||
2023-03-20 | Implement Smrnmi extension | Andrew Waterman | 1 | -0/+15 | |
We don't model any sources of RNMI, so this is mostly vestigial. | |||||
2023-02-21 | Remove redundant RVE related check in cm.mva01s and cm.mvsa01 | Weiwei Li | 2 | -6/+0 | |
r1s/r2s > 16 when r1sc/r1sc >2. This will also trigger illegal instruction exception by CHECK_REG if RVE is enabled | |||||
2023-02-21 | Add r1s != r2s check for cm.mvsa01 | Weiwei Li | 1 | -0/+1 | |
2023-02-21 | Update fields name for sreg1/sreg2 | Weiwei Li | 2 | -6/+6 | |
2023-01-31 | Zicond: implement Zicond (conditional integer operations) | Philipp Tomsich | 2 | -0/+4 | |
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details. | |||||
2022-12-05 | Merge pull request #1162 from riscv-software-src/sfence | Andrew Waterman | 2 | -3/+2 | |
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode | |||||
2022-12-05 | SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes | Andrew Waterman | 1 | -0/+1 | |
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213 | |||||
2022-12-05 | Simplify implementation of SFENCE.W.INVAL | Andrew Waterman | 1 | -3/+1 | |
For Spike, this instruction merely performs exception checks, just like SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR. | |||||
2022-11-28 | Merge pull request #1156 from plctlab/plct-zce-fix | Andrew Waterman | 1 | -1/+1 | |
Fix support for Zc* | |||||
2022-11-28 | Fix field extract for jvt.base | Weiwei Li | 1 | -1/+1 | |
2022-11-21 | When resuming from debug mode, clear mstatus.MPRV if the new privilege mode ↵ | YenHaoChen | 1 | -0/+2 | |
is less than M-mode (#1149) | |||||
2022-11-17 | add support for zcmt | Weiwei Li | 1 | -0/+23 | |
add suport for jvt: Table entries follow the current data endianness | |||||
2022-11-17 | add support for zcmp | Weiwei Li | 6 | -0/+50 | |
2022-11-17 | add support for zcb | Weiwei Li | 12 | -0/+30 | |
2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 35 | -43/+39 | |
2022-10-25 | Change remaining vector FP16 instructions to require Zvfh | Andrew Waterman | 15 | -44/+44 | |
...as opposed to Zfh. | |||||
2022-10-25 | Change SEW=16 vfncvt.f.f.w and vfwcvt.f.f.v to require Zvfhmin | Andrew Waterman | 2 | -12/+12 | |
...as opposed to Zfh. | |||||
2022-10-19 | Template-ize stores | Andrew Waterman | 13 | -15/+15 | |
2022-10-19 | Template-ize loads | Andrew Waterman | 16 | -18/+18 | |
2022-10-19 | Template-ize AMOs | Andrew Waterman | 18 | -18/+18 | |
2022-10-19 | DRY in store-conditional instructions | Andrew Waterman | 2 | -12/+2 | |
2022-10-19 | Template-ize hypervisor loads and stores | Andrew Waterman | 13 | -13/+13 | |
2022-10-19 | Fix imprecise exception on LR to MMIO space | Andrew Waterman | 2 | -6/+2 | |
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise. | |||||
2022-10-11 | Set tval on illegal subforms of aes64ks1i | Andrew Waterman | 1 | -4/+1 | |
h/t @YenHaoChen | |||||
2022-10-04 | Fix unused-variable warnings in P-extension instruction definitions | Andrew Waterman | 1 | -1/+0 | |
2022-10-04 | Suppress unused-variable warnings in vector instruction definitions | Andrew Waterman | 6 | -10/+0 | |
2022-10-04 | Suppress unused-variable warnings in AES code | Andrew Waterman | 1 | -2/+2 | |
2022-10-04 | Suppress most unused variable warnings | Andrew Waterman | 2 | -2/+2 | |
2022-09-28 | Fix vmv.x.s for RV32 | Andrew Waterman | 1 | -8/+9 | |
The Spike internals require that, when XLEN is narrower than reg_t, values be sign-extended to the width of reg_t. | |||||
2022-09-08 | Remove unnecessary argument alu(always false) from macro | Weiwei Li | 3 | -3/+3 | |
require_vector_novtype | |||||
2022-09-06 | fix comment in definition of vmv<nf>r.v | Andrew Waterman | 1 | -1/+1 | |
2022-09-06 | vmv<nf>r.v depends on vtype, and therefore should check vill | Andrew Waterman | 1 | -1/+1 | |
2022-08-22 | Fix redundant loops when calculating vrgather.vi. (#1072) | yangcheng | 1 | -6/+0 | |
2022-08-12 | Remove unused code in vsmul* (#1069) | ksco | 2 | -19/+2 | |
2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 47 | -56/+56 | |
Add space between ')' and '{' | |||||
2022-08-04 | Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵ | liweiwei | 87 | -193/+193 | |
instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com> | |||||
2022-08-01 | WFI condition fix | Canberk Topal | 1 | -1/+3 | |
Before this commit Spike was requiring S mode privilege even without S mode implemented. This commit fixes it. Signed-off-by: Canberk Topal <ctopal@lowrisc.org> | |||||
2022-07-28 | Fix overflow issue of p-ext multiply instructions (#1053) | ChunPing Chung | 8 | -8/+8 | |
2022-05-19 | Move ebreak* logic from take_trap into instructions. (#1006) | Tim Newsome | 2 | -2/+16 | |
Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode. | |||||
2022-04-10 | Adjust the access index of vs2 to zero in vmv_x_s.h (#969) | Brandon Wu | 1 | -21/+17 | |
2022-04-07 | Rename processor_t::set_csr to put_csr to fix build on RISC-V | Andrew Waterman | 7 | -7/+7 | |
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write. | |||||
2022-03-29 | Fix start byte for vmv<nf>r.v (#959) | liweiwei90 | 1 | -3/+4 | |
'The instructions operate as if EEW=SEW.EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte should take sew into acount when vstart != 0 | |||||
2022-03-12 | Construct an isa_parser_t and pass it to processor_t constructor | Rupert Swarbrick | 1 | -2/+2 | |
This is a minor change, turning processor_t from a child class of isa_parser_t into a class that contains an isa_parser_t as a field. The point is that it is a step toward separating out "configuration" (and ISA string parsing) from processor state. This should be helpful for rejigging things so that we construct more from a supplied device tree. | |||||
2022-02-27 | perform hstatus probe/update for sret only when H extension enabled. (#934) | Neel Gala | 1 | -5/+6 | |
* perform hstatus probe/update for sret only when H extension enabled. * added missing parenthesis | |||||
2022-02-23 | csr: hyper: fix mstatus.mpp after mret | Chih-Min Chao | 1 | -1/+1 | |
By spec 3.1.6.1 (original behavior) "x PP is set to the least-privileged supported mode (U if U-mode is implemented, else M)" By spec 8.6.4 (h-extension) "MRET first determines what the new privilege mode will be according to the values of MPP and MPV in mstatus or mstatush, as encoded in Table 8.8. MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> |