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2022-02-17Split Xbitmanip into its proposed component extensions (#918)Rupert Swarbrick59-59/+69
Before this patch, spike just had an "Xbitmanip" extension which covered everything in the proposed bitmanip extension that hadn't been ratified. The problem is that if you want to model (or verify) a processor that targetted just some of the proposed bitmanip extension, you couldn't configure Spike to do that. For example, the lowRISC Ibex processor has several different configurations. The "balanced" configuration targetted Zba, Zbb, Zbs, Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified, we'll now be able to use an ISA string like rv32imc_Zba_Zbb_Zbs_XZbf_XZbt and Spike will correctly fail to decode instructions like 'bcompress', which would have been decoded with Xbitmanip. This patch adds a new custom extension name for each part of the extension that wasn't fully ratified. These have an 'X' prefix so, for example, the bit permutation instructions that were proposed as Zbp can be found under XZbp. Specifying "Xbitmanip" gets all of these extensions, so its behaviour should be unchanged. Note that the slo(i) / sro(i) instructions have been moved from the proposed Zbb to XZbp. This matches a comment in the Change History section of v0.93 of the bitmanip spec: it seems that the authors forgot to also move them in Table 2.1 (which gives the lists of instructions for each extension). This change won't break anything that currently exists, but it took quite a while to figure out what was going on so I thought I'd leave a breadcrumb trail for the next engineer! The bulk of the patch is just defining some more entries in the isa_extension_t enum and rewriting each of the instructions to depend on the relevant entry. This is mostly a straight textual replacement but it's slightly more complicated for things like the "pack" instruction that are defined by several different proposed extensions.
2022-01-30add instructions function for cmoliweiwei5-0/+22
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
2021-12-27Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)Yueh-Ting (eop) Chen4-4/+4
Refer to rvv-spec v1.0-rc2
2021-12-17Merge pull request #881 from eopXD/simplify-float-convertAndrew Waterman22-407/+177
Simplify float convert instructions
2021-12-09P-ext v.0.9.11. update (#883)marcfedorow4-4/+4
2021-12-09Simplfy vfmv_v_f (#884)Yueh-Ting (eop) Chen1-30/+3
2021-12-09Simplify vfwcvteopXD7-156/+62
2021-12-09Simplfy vfcvteopXD6-66/+36
2021-12-09Simplify vfncvteopXD8-182/+76
2021-12-08Have vd.v unexposedeopXD1-3/+3
2021-12-07Add 'Zfhmin' extension (#880)Tsukasa #01 (a4lg)10-10/+10
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating point) extension, consisting only of data transfer and conversion instructions. This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin" as a multi-letter extension and adjusts feature gate for data transfer / conversion instructions. * FLH / FSH * FMV.X.H / FMV.H.X * FCVT.S.H / FCVT.H.S * FCVT.D.H / FCVT.H.D (if 'D' extension is also present) * FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
2021-12-07Merge pull request #879 from eopXD/simply-instsAndrew Waterman17-109/+29
Simply floating point parameters and merge operations
2021-12-07Simplify vadc and vsbc (#876)Yueh-Ting (eop) Chen5-30/+5
2021-12-07Merge pull request #868 from eopXD/simplify-narrowing-instAndrew Waterman12-18/+18
Simplify narrowing instruction
2021-12-07Simplify vwmulsu_vv and vwmulsu_vx (#861)Yueh-Ting (eop) Chen2-22/+2
Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX
2021-12-08Simplify vmerge, vfmergeeopXD7-73/+9
2021-12-08Simplify floating point compare instructionseopXD10-30/+20
2021-12-08Simply parameters for floating-point instructionseopXD1-9/+3
2021-12-06Simplify vmadc and vmsbc (#877)Yueh-Ting (eop) Chen5-45/+5
2021-11-30Simplify mulhsu (#870)Yueh-Ting (eop) Chen2-72/+4
2021-11-29Revert "Simplify vmulhsu (#863)"Andrew Waterman2-6/+72
This reverts commit 1a5b2d9dda8741e98444289135e0fbcb2c3f5740, which is buggy (the vs1 argument is being sign-extended).
2021-11-28Have nclip_{wv/wx/wi} use different macroseopXD6-12/+12
This allows them to share PARAM macro with narrowing right-shift instructions. Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it. (Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)
2021-11-28Eliminate redundant parameters for narrowing integer right shift instructionseopXD6-6/+6
2021-11-27Simplify single-width averaging add and subtract (#867)Yueh-Ting (Eop) Chen8-8/+8
2021-11-26Simplify vmulhsu (#863)Yueh-Ting (Eop) Chen2-72/+6
2021-11-04Report proper GVA bit on breakpoint trapsScott Johnson2-2/+2
2021-11-04Add gva field to trap_breakpointScott Johnson2-2/+2
So I can fix breakpoints next to properly report gva.
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen4-0/+0
Krypto 1.0 changes: Entropy source CSR, name. List scalar crypto instruction groupings, as there is no single K extension. Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
2021-10-20Fixup of #830 (#839)marcfedorow1-1/+0
2021-10-18Delete SHAMT check in pack (#838)liweiwei901-1/+0
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow82-126/+77
* Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix
2021-10-06When mstatus.VS exists, P-extension instructions must respect itScott Johnson133-0/+133
Any instruction that may write vxsat will take an illegal instruction exception if mstatus.VS exists and is Off. In Spike today, mstatus.VS exists iff misa.V=1, which is true iff the --isa string enables the V extension. I went through the riscv-p-spec looking for "OV = 1" and added this behavior to every matching instruction. See #823 for discussion.
2021-10-06Add missing newlines at end of fileScott Johnson324-324/+324
2021-09-29Convert vl to csr_tScott Johnson9-10/+10
Adds commit log events for vl to many vector instructions.
2021-09-29Convert vstart to csr_tScott Johnson18-37/+37
Adds commit log events for vstart to many vector instructions.
2021-09-29Be consistent in use of P_SET_OV macro for setting vxsatScott Johnson18-22/+21
2021-09-27Convert frm & fflags to csr_tScott Johnson8-18/+18
Adds proper logging of fflags on FP arithmetic ops.
2021-09-26Convert dcsr to csr_tScott Johnson1-2/+2
2021-09-26Convert dpc to csr_tScott Johnson1-1/+1
2021-09-24Actually fix SRET clearing MPRVAndrew Waterman1-4/+4
Reverts 12131ba08c90045efae33067b79d15f4d2fb63f0
2021-09-24Fix SRET clearing MPRVAndrew Waterman1-2/+2
Attempting to clear MPRV via sstatus is fruitless. Use mstatus instead.
2021-09-24Clear MPV on MRET and (when V=0) clear SPV on SRETAndrew Waterman2-2/+7
2021-09-14Added insn overlapping (bitmanip / krypto) (#801)marcfedorow20-36/+34
2021-09-09Splitted K-ext to zedsMark Fedorov29-29/+29
2021-09-08Convert hstatus to csr_t familyScott Johnson16-17/+17
2021-09-08Rename supports_extension() to extension_enabled()Scott Johnson17-42/+42
Because this checks the dynamic run-time state of misa, let's use the same language as the misa spec (enabled vs disabled). Calling it supports_extension() could be confused for a check of the static configuration of Spike (i.e. the --isa string), which it was not.
2021-09-08Convert mstatus into csr_t familyScott Johnson5-5/+5
Step 3 of plan described in csrs.h.
2021-09-08Convert sret to use sstatusScott Johnson1-2/+2
Part of step 2 of plan described in csrs.h.
2021-09-08Convert sepc & vsepc to use csr_t familyScott Johnson1-1/+1
Fixes commitlog of `csrw sepc` in VS-mode to properly report vsepc instead of sepc.
2021-09-08Implement epc_csr_t and use it for mepc registerScott Johnson1-1/+1
The commitlog will now properly log writes to mepc that occur when a trap is taken. sepc and vsepc will also use this new data type; coming soon.
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