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Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
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prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
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Refer to rvv-spec v1.0-rc2
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Simplify float convert instructions
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Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating
point) extension, consisting only of data transfer and conversion
instructions.
This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin"
as a multi-letter extension and adjusts feature gate for
data transfer / conversion instructions.
* FLH / FSH
* FMV.X.H / FMV.H.X
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D (if 'D' extension is also present)
* FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
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Simply floating point parameters and merge operations
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Simplify narrowing instruction
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Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX
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This reverts commit 1a5b2d9dda8741e98444289135e0fbcb2c3f5740,
which is buggy (the vs1 argument is being sign-extended).
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This allows them to share PARAM macro with narrowing right-shift instructions.
Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it.
(Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)
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So I can fix breakpoints next to properly report gva.
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Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.
Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
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* Added ZMMUL extension
* Splitted P-ext to its zeds
* Typo fix
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Any instruction that may write vxsat will take an illegal instruction
exception if mstatus.VS exists and is Off.
In Spike today, mstatus.VS exists iff misa.V=1, which is true iff the
--isa string enables the V extension.
I went through the riscv-p-spec looking for "OV = 1" and added this
behavior to every matching instruction.
See #823 for discussion.
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Adds commit log events for vl to many vector instructions.
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Adds commit log events for vstart to many vector instructions.
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Adds proper logging of fflags on FP arithmetic ops.
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Reverts 12131ba08c90045efae33067b79d15f4d2fb63f0
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Attempting to clear MPRV via sstatus is fruitless. Use mstatus instead.
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Because this checks the dynamic run-time state of misa, let's use the
same language as the misa spec (enabled vs disabled).
Calling it supports_extension() could be confused for a check of the
static configuration of Spike (i.e. the --isa string), which it was
not.
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Step 3 of plan described in csrs.h.
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Part of step 2 of plan described in csrs.h.
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Fixes commitlog of `csrw sepc` in VS-mode to properly report vsepc
instead of sepc.
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The commitlog will now properly log writes to mepc that occur when a
trap is taken.
sepc and vsepc will also use this new data type; coming soon.
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