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AgeCommit message (Expand)AuthorFilesLines
2023-04-14Add support for new instructions of Zvfbfmin extensionWeiwei Li2-0/+10
2023-04-14Add support for new instructions of Zfbfmin extensionWeiwei Li2-0/+11
2023-04-03Implement Zfa.Philipp Tomsich33-0/+420
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+15
2023-02-21Remove redundant RVE related check in cm.mva01s and cm.mvsa01Weiwei Li2-6/+0
2023-02-21Add r1s != r2s check for cm.mvsa01Weiwei Li1-0/+1
2023-02-21Update fields name for sreg1/sreg2Weiwei Li2-6/+6
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich2-0/+4
2022-12-05Merge pull request #1162 from riscv-software-src/sfenceAndrew Waterman2-3/+2
2022-12-05SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modesAndrew Waterman1-0/+1
2022-12-05Simplify implementation of SFENCE.W.INVALAndrew Waterman1-3/+1
2022-11-28Merge pull request #1156 from plctlab/plct-zce-fixAndrew Waterman1-1/+1
2022-11-28Fix field extract for jvt.baseWeiwei Li1-1/+1
2022-11-21When resuming from debug mode, clear mstatus.MPRV if the new privilege mode i...YenHaoChen1-0/+2
2022-11-17add support for zcmtWeiwei Li1-0/+23
2022-11-17add support for zcmpWeiwei Li6-0/+50
2022-11-17add support for zcbWeiwei Li12-0/+30
2022-11-17add support for zca zcd and zcfWeiwei Li35-43/+39
2022-10-25Change remaining vector FP16 instructions to require ZvfhAndrew Waterman15-44/+44
2022-10-25Change SEW=16 vfncvt.f.f.w and vfwcvt.f.f.v to require ZvfhminAndrew Waterman2-12/+12
2022-10-19Template-ize storesAndrew Waterman13-15/+15
2022-10-19Template-ize loadsAndrew Waterman16-18/+18
2022-10-19Template-ize AMOsAndrew Waterman18-18/+18
2022-10-19DRY in store-conditional instructionsAndrew Waterman2-12/+2
2022-10-19Template-ize hypervisor loads and storesAndrew Waterman13-13/+13
2022-10-19Fix imprecise exception on LR to MMIO spaceAndrew Waterman2-6/+2
2022-10-11Set tval on illegal subforms of aes64ks1iAndrew Waterman1-4/+1
2022-10-04Fix unused-variable warnings in P-extension instruction definitionsAndrew Waterman1-1/+0
2022-10-04Suppress unused-variable warnings in vector instruction definitionsAndrew Waterman6-10/+0
2022-10-04Suppress unused-variable warnings in AES codeAndrew Waterman1-2/+2
2022-10-04Suppress most unused variable warningsAndrew Waterman2-2/+2
2022-09-28Fix vmv.x.s for RV32Andrew Waterman1-8/+9
2022-09-08Remove unnecessary argument alu(always false) from macroWeiwei Li3-3/+3
2022-09-06fix comment in definition of vmv<nf>r.vAndrew Waterman1-1/+1
2022-09-06vmv<nf>r.v depends on vtype, and therefore should check villAndrew Waterman1-1/+1
2022-08-22Fix redundant loops when calculating vrgather.vi. (#1072)yangcheng1-6/+0
2022-08-12Remove unused code in vsmul* (#1069)ksco2-19/+2
2022-08-10Add space between if/while/switch and '('Weiwei Li47-56/+56
2022-08-04Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instruc...liweiwei87-193/+193
2022-08-01WFI condition fixCanberk Topal1-1/+3
2022-07-28Fix overflow issue of p-ext multiply instructions (#1053)ChunPing Chung8-8/+8
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome2-2/+16
2022-04-10Adjust the access index of vs2 to zero in vmv_x_s.h (#969)Brandon Wu1-21/+17
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman7-7/+7
2022-03-29Fix start byte for vmv<nf>r.v (#959)liweiwei901-3/+4
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-2/+2
2022-02-27perform hstatus probe/update for sret only when H extension enabled. (#934)Neel Gala1-5/+6
2022-02-23csr: hyper: fix mstatus.mpp after mretChih-Min Chao1-1/+1
2022-02-17Split Xbitmanip into its proposed component extensions (#918)Rupert Swarbrick59-59/+69
2022-01-30add instructions function for cmoliweiwei5-0/+22
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