| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-02-19 | Raise illegal instruction instead of virtual instruction on WFI when TW=1 in ... | YenHaoChen | 1 | -5/+3 |
| 2022-08-01 | WFI condition fix | Canberk Topal | 1 | -1/+3 |
| 2021-09-08 | Convert hstatus to csr_t family | Scott Johnson | 1 | -1/+1 |
| 2021-09-08 | Convert mstatus into csr_t family | Scott Johnson | 1 | -1/+1 |
| 2020-09-24 | correctly respect mstatus.TW and hstatus.VTW | Andrew Waterman | 1 | -2/+9 |
| 2020-09-21 | Raise virtual-instruction traps correctly for WFI/SRET/SFENCE | Andrew Waterman | 1 | -2/+2 |
| 2020-07-09 | Implement hypervisor CSRs read/write | Anup Patel | 1 | -0/+2 |
| 2018-04-30 | Only break out of the simulator loop on WFI, not on CSR writes | Andrew Waterman | 1 | -1/+1 |
| 2017-03-13 | Implement mstatus.TW, mstatus.TVM, and mstatus.TSR | Andrew Waterman | 1 | -0/+1 |
| 2017-02-20 | serialize simulator on wfi | Andrew Waterman | 1 | -1/+1 |
| 2015-05-09 | Upgrade to privileged architecture 1.7 | Andrew Waterman | 1 | -0/+1 |
 |
index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |