| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-12-06 | Simplify vmadc and vmsbc (#877) | Yueh-Ting (eop) Chen | 1 | -9/+1 |
| 2021-08-09 | rvv fix 2021-08-09 (#768) | Chih-Min Chao | 1 | -1/+1 |
| 2020-05-28 | rvv: remove vmlen | Chih-Min Chao | 1 | -1/+1 |
| 2020-02-14 | rvv: vsbc/vmsbc behavior of the sub order | Max Lin | 1 | -1/+1 |
| 2019-12-20 | rvv: fix vmadc/vmsbc | Chih-Min Chao | 1 | -1/+1 |
| 2019-11-11 | rvv: fix reg checking for vmadc/vmsbc | Chih-Min Chao | 1 | -1/+0 |
| 2019-06-18 | rvv: add integer/fixed-point/mask/reduction/permutation instructions | Chih-Min Chao | 1 | -0/+14 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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