rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-25	Change remaining vector FP16 instructions to require Zvfh	Andrew Waterman	1	-1/+1
2022-08-10	Add space between if/while/switch and '('	Weiwei Li	1	-1/+1
2021-09-29	Convert vstart to csr_t	Scott Johnson	1	-1/+1
2021-09-27	Convert frm & fflags to csr_t	Scott Johnson	1	-1/+1
2021-09-08	Rename supports_extension() to extension_enabled()	Scott Johnson	1	-3/+3
2020-08-31	rvv: check invalid frm for floating operations	Chih-Min Chao	1	-0/+1
2020-08-03	rvv: add 'vstartalu" option to --varch arugment	Chih-Min Chao	1	-1/+1
2020-05-04	rvv: fp16: support element movement instructions	Chih-Min Chao	1	-9/+16
2020-03-12	rvv: fix vfmv.s.f and vfmv.f.s	Chih-Min Chao	1	-0/+2
2020-01-09	rvv: refinve vfmv to support float64	Chih-Min Chao	1	-7/+1
2019-11-11	rvv: add reg checking for specifial instructions	Chih-Min Chao	1	-1/+0
2019-07-19	Check vtype.vill for all vector instructions except vsetvl[i]	Andrew Waterman	1	-0/+1
2019-07-19	Check for F extension in vfmv instructions	Andrew Waterman	1	-0/+1
2019-07-19	Avoid relying on sizeof long	Andrew Waterman	1	-1/+1
2019-06-18	rvv: add floating-point instructions	Chih-Min Chao	1	-0/+33