| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2020-05-04 | rvv: fp16: support .vv instructions | Chih-Min Chao | 1 | -0/+3 | |
| Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2020-01-09 | rvv: add vfxxx.vv float64 suuport | Chih-Min Chao | 1 | -0/+3 | |
| Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2019-06-18 | rvv: add floating-point instructions | Chih-Min Chao | 1 | -0/+5 | |
| based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> | |||||
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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