| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 |
| 2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 1 | -0/+1 |
| 2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -1/+1 |
| 2010-09-22 | [sim] fixed bug in which shift operands were reversed | Andrew Waterman | 1 | -1/+1 |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 |
| 2010-09-12 | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 1 | -0/+1 |
| 2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 1 | -1/+0 |
| 2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -0/+1 |
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index : rocket-tools/riscv-isa-sim.git | |
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