rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2022-12-05	Simplify implementation of SFENCE.W.INVAL	Andrew Waterman	1	-3/+1
	For Spike, this instruction merely performs exception checks, just like SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR.
2021-08-29	ext: apply Svinval sub-extesion check to related instructions	Chih-Min Chao	1	-0/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-07-20	Priv virtual memory updates (#750)	Daniel Lustig	1	-0/+2
	* Priv virtual memory updates * Priv 1.12 requires page faults when the address translation process reaches a PTE with any reserved bit set * Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since Spike is sequentially consistent and does not model PMAs) * Add Svinval instructions Even though I updated riscv-opcodes separately, I merged the new defines into riscv/encoding.h manually, because riscv-opcodes seems to be a step ahead of riscv-isa-sim for a few vector opcodes, causing conflicts when regenerating encoding.h... If that gets fixed, and encoding.h gets regenerated automatically, I can remove it from this PR to avoid conflicts. * Svinval: use #include rather than copying code ..for the Svinval functions that are implemented in ways that just mimic SFENCE/HFENCE instructions Thanks to @aswaterman for the suggestion