rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-05-23	zicflip: fix [ms]ret behavior	Chih-Min Chao	1	-1/+1
2024-03-06	Zicfilp: Preserve expected landing pad state on traps	Ming-Yi Lai	1	-0/+4
2024-01-12	Add missing log commit of mstatush	demin.han	1	-0/+1
2024-01-11	Refactor put_csr to direct write	demin.han	1	-1/+1
2023-05-25	Refactor set_privilege to subsume set_virt	Andrew Waterman	1	-2/+1
2022-04-07	Rename processor_t::set_csr to put_csr to fix build on RISC-V	Andrew Waterman	1	-1/+1
2022-02-23	csr: hyper: fix mstatus.mpp after mret	Chih-Min Chao	1	-1/+1
2021-09-24	Clear MPV on MRET and (when V=0) clear SPV on SRET	Andrew Waterman	1	-0/+1
2021-09-08	Convert mstatus into csr_t family	Scott Johnson	1	-1/+1
2021-09-08	Implement epc_csr_t and use it for mepc register	Scott Johnson	1	-1/+1
2021-06-02	pmp: mstatus.mprv should be clear if mpp is not M-mode	Chih-Min Chao	1	-0/+2
2020-07-09	Implement hypervisor CSRs read/write	Anup Patel	1	-1/+3
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	1	-1/+1
2017-02-01	Set xPIE=1 on xRET	Andrew Waterman	1	-1/+1
2016-04-19	Split ERET into URET, SRET, HRET, MRET	Andrew Waterman	1	-0/+9
2015-03-17	Merge [shm]call into ecall, [shm]ret into eret	Andrew Waterman	1	-3/+0
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-0/+3