| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-01-02 | On misaligned fetch, set EPC to target, not branch itself | Andrew Waterman | 1 | -1/+2 |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2013-09-10 | Add rd field to JAL; drop J | Andrew Waterman | 1 | -1/+1 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 |
| 2011-06-11 | [xcc] instructions now set PC explicitly | Andrew Waterman | 1 | -1/+1 |
| 2010-12-27 | [sim] cleaned up handling of link register | Andrew Waterman | 1 | -1/+1 |
| 2010-11-21 | [xcc, sim, pk] link register is now x1 | Andrew Waterman | 1 | -1/+1 |
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+2 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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