| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-08-04 | Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instruc... | liweiwei | 1 | -2/+2 |
| 2017-04-10 | Implement new FP encoding | Andrew Waterman | 1 | -1/+1 |
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -0/+1 |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 |
| 2011-02-15 | [xcc,opcodes,pk,sim] krste's re-renaming spree | Andrew Waterman | 1 | -0/+2 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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