Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2022-04-07 | Rename processor_t::set_csr to put_csr to fix build on RISC-V | Andrew Waterman | 1 | -1/+1 | |
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write. | |||||
2020-09-20 | Don't throw virtual instruction exceptions for unimplemented CSRs | Andrew Waterman | 1 | -1/+1 | |
2020-09-15 | Populate tval registers on illegal-/virtual-instruction traps | Andrew Waterman | 1 | -1/+1 | |
2018-03-03 | Implement clearing-misa.C-while-PC-is-misaligned proposal | Andrew Waterman | 1 | -0/+1 | |
See https://github.com/riscv/riscv-isa-manual/pull/139 Not adopted yet, but I'm putting the implementation here for reference. | |||||
2016-05-21 | Some bugfixes for CSR reading and setting FS for fflags updates (#43) | Andy Wright | 1 | -2/+5 | |
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0 * Dirty fp state when setting new fp exceptions * Set FS to dirty for all non-zero fflags writes. | |||||
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -2/+2 | |
Sorry, everyone. | |||||
2015-02-08 | Use xlen, not xprlen, to refer to x-register width | Andrew Waterman | 1 | -1/+1 | |
2014-11-30 | Implement timer faithfully | Andrew Waterman | 1 | -1/+3 | |
rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed. | |||||
2014-03-18 | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | Andrew Waterman | 1 | -1/+1 | |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -1/+1 | |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -0/+2 | |