| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-04-07 | Rename processor_t::set_csr to put_csr to fix build on RISC-V | Andrew Waterman | 1 | -1/+1 |
| 2020-09-20 | Don't throw virtual instruction exceptions for unimplemented CSRs | Andrew Waterman | 1 | -1/+1 |
| 2020-09-15 | Populate tval registers on illegal-/virtual-instruction traps | Andrew Waterman | 1 | -1/+1 |
| 2018-03-03 | Implement clearing-misa.C-while-PC-is-misaligned proposal | Andrew Waterman | 1 | -0/+1 |
| 2016-05-21 | Some bugfixes for CSR reading and setting FS for fflags updates (#43) | Andy Wright | 1 | -2/+5 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -2/+2 |
| 2015-02-08 | Use xlen, not xprlen, to refer to x-register width | Andrew Waterman | 1 | -1/+1 |
| 2014-11-30 | Implement timer faithfully | Andrew Waterman | 1 | -1/+3 |
| 2014-03-18 | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | Andrew Waterman | 1 | -1/+1 |
| 2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -1/+1 |
| 2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -0/+2 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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