| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 1 | -1/+1 |
| 2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -6/+1 |
| 2015-05-31 | New RV64C proposal | Andrew Waterman | 1 | -1/+6 |
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -1/+1 |
| 2015-03-30 | Implement RVC draft | Andrew Waterman | 1 | -0/+2 |
| 2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -10/+0 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+10 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -10/+0 |
| 2011-06-11 | [xcc] instructions now set PC explicitly | Andrew Waterman | 1 | -3/+3 |
| 2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -1/+9 |
| 2011-04-11 | [xcc,sim,opcodes] more rvc instructions and bug fixes | Andrew Waterman | 1 | -1/+1 |
| 2011-04-09 | [xcc,pk,sim,opcodes] added first RVC instruction | Andrew Waterman | 1 | -0/+2 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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