| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 1 | -1/+1 |
| 2015-04-02 | Simplify RV32 comparisons | Andrew Waterman | 1 | -1/+1 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+2 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -2/+0 |
| 2011-06-11 | [xcc] instructions now set PC explicitly | Andrew Waterman | 1 | -1/+1 |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -1/+1 |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -1/+1 |
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+2 |
 |
index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |