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AgeCommit message (Expand)AuthorFilesLines
2020-07-08Extend trap classes to pass more informationAnup Patel1-1/+1
2020-07-02commitlog: support csr accessChih-Min Chao1-1/+5
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-2/+6
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
2020-06-04rvv: fix compilation warningChih-Min Chao1-1/+1
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-1/+5
2020-05-26Report haltgroup halt cause, per the debug spec. (#473)Tim Newsome1-1/+3
2020-04-29rvv: commitlog: report status when memory trap occurs in vector load/storeChih-Min Chao1-6/+25
2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick1-27/+37
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao1-7/+14
2020-03-09commitlog: enhance vector dumpChih-Min Chao1-5/+14
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-15/+55
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-7/+9
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-5/+11
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-5/+14
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+3
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-3/+3
2019-06-18rvv: extend interactive debugChih-Min Chao1-1/+0
2019-04-02Implement debug hasel support (#287)Tim Newsome1-7/+10
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome1-3/+5
2018-04-30Fix commit log for serializing instructionsAndrew Waterman1-1/+1
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman1-1/+2
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-1/+0
2018-03-09Fix single stepping csrrw instructions (#178)Tim Newsome1-8/+7
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-1/+0
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-0/+1
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman1-16/+2
2017-12-11Make progbuf a run-time option.Tim Newsome1-3/+1
2017-11-20Fix commitlog. (#162)Christopher Celio1-5/+8
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman1-15/+42
2017-09-21Fix comment typo. (#126)Tim Newsome1-1/+1
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...Megan Wachs1-5/+8
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-2/+2
2017-02-23Implement halt request.Tim Newsome1-2/+1
2017-02-21Don't waste time spinning in place in debug modeTim Newsome1-4/+7
2017-02-20serialize simulator on wfiAndrew Waterman1-1/+1
2017-02-02Fix interrupt delegation for coprocessorsAndrew Waterman1-1/+1
2016-12-15Fix single stepping over faulting instructions. (#80)Tim Newsome1-0/+5
2016-12-01Added comments about the modified Duff's Device in execute.cc (#77)Andy Wright1-0/+37
2016-08-25partially update spike to newer debug specAndrew Waterman1-2/+6
2016-08-25Fix spike interactive (-d) modeAndrew Waterman1-5/+3
2016-08-22Implement address and data triggers.Tim Newsome1-2/+32
2016-07-13Fix single step over csrw instructions. (#57)Tim Newsome1-5/+9
2016-05-23Remove obsolete TODO.Tim Newsome1-3/+0
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-7/+8
2016-05-23Fix reading CSRs.Tim Newsome1-4/+0
2016-05-23Single step appears to work.Tim Newsome1-2/+19
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