rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-08-31	rvv: add reciprocal instructions	Chih-Min Chao	1	-0/+6
2020-08-27	rvv: remove quad instructions	Chih-Min Chao	1	-12/+0
2020-08-04	Merge pull request #521 from chihminchao/op-hypvervisor	Andrew Waterman	1	-48/+48
2020-08-03	op: hyperviosr: fix exception code and name	Chih-Min Chao	1	-3/+3
2020-08-03	op: rearrange hypbervisor op/csr/cause	Chih-Min Chao	1	-46/+46
2020-08-03	op: rvv: fix pesudo code instructions	Chih-Min Chao	1	-3/+3
2020-07-29	rvv: add vrgatherei16.vv	Chih-Min Chao	1	-0/+3
2020-07-29	rvv: add new whole reg load/store instructions	Chih-Min Chao	1	-3/+69
2020-07-29	rvv: op: rearrange some instruction since generation order change	Chih-Min Chao	1	-36/+36
2020-07-29	rvv: op: fix amo naming	Chih-Min Chao	1	-108/+108
2020-07-09	Implement hypervisor CSRs read/write	Anup Patel	1	-3/+14
2020-07-08	Add hypervisor extension related CSR and instruction defines	Anup Patel	1	-6/+81
2020-06-16	zfh: op: add scalar opcode	Chih-Min Chao	1	-0/+108
2020-05-28	rvv: add new explicit eew load/store instructions	Chih-Min Chao	1	-134/+194
2020-05-28	rvv: add amo instructions	Chih-Min Chao	1	-54/+108
2020-05-28	rvv: add new singed/unsiged extension instructions	Chih-Min Chao	1	-0/+18
2020-05-28	rvv: op: change funary op	Chih-Min Chao	1	-47/+47
2020-05-26	Report haltgroup halt cause, per the debug spec. (#473)	Tim Newsome	1	-0/+1
2020-04-24	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	1	-0/+6
2020-04-20	rvv: add float conversion for rtz variants	Chih-Min Chao	1	-0/+18
2020-04-20	Move vxrm/vxsat from fcsr to vcsr	Andrew Waterman	1	-0/+2
2020-04-09	op: update CSR	Chih-Min Chao	1	-2/+28
2020-03-09	op: rvv: update encoding	Chih-Min Chao	1	-315/+372
2020-02-28	Add do-nothing support for mcountinhibit CSR	Rupert Swarbrick	1	-0/+2
2020-01-13	rvv: add vmv[1248]r.v	Chih-Min Chao	1	-0/+12
2019-12-20	rvv: support new mstatus.vs field defined in v0.8	Chih-Min Chao	1	-0/+2
2019-12-20	rvv: replace vn suffic by 'w'	Chih-Min Chao	1	-36/+36
2019-12-20	rvv: add load/store whole register instructions	Chih-Min Chao	1	-0/+6
2019-12-20	rvv: rename vfncvt suffix and add rod rouding type	Chih-Min Chao	1	-18/+18
2019-12-20	rvv: add quad insn and new vlenb csr	Chih-Min Chao	1	-21/+23
2019-11-15	Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu	Andrew Waterman	1	-43/+55
2019-10-29	rvv: remove vmford	Chih-Min Chao	1	-6/+0
2019-07-19	vext.x.v -> vmv.x.s; unary operation encoding changes	Andrew Waterman	1	-13/+13
2019-07-05	vmfirst/vmpopc have been renamed to vfirst/vpopc	Andrew Waterman	1	-32/+43
2019-06-14	rvv: add the v-spec-0.7.1 encoding	Chih-Min Chao	1	-11/+1218
2017-11-27	Rename badaddr to tval	Andrew Waterman	1	-4/+4
2017-11-27	Rename sptbr to satp	Andrew Waterman	1	-16/+16
2017-05-05	UXL=SXL=MXL	Andrew Waterman	1	-0/+3
2017-04-25	FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X	Andrew Waterman	1	-6/+6
2017-04-25	Remove hret instruction	Andrew Waterman	1	-3/+0
2017-03-31	update encoding.h to get PMP updates	Yunsup Lee	1	-5/+6
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	1	-6/+12
2017-03-23	Require little-endian host	Andrew Waterman	1	-0/+10
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	1	-0/+2
2017-03-21	riscv: remove dependency on num_cores	Wesley W. Terpstra	1	-3/+0
2017-03-20	PUM -> SUM; expose MXR to S-mode	Andrew Waterman	1	-2/+3
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	1	-0/+40
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	1	-0/+3
2017-02-26	Sv57 and Sv64 are not spec'd yet	Andrew Waterman	1	-14/+9
2017-02-25	New counter enable scheme	Andrew Waterman	1	-20/+8