rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-05-23	Move debug rom link map to the right place.	Tim Newsome	2	-2/+2
2016-05-23	Use fence.i in Debug ROM.	Tim Newsome	2	-9/+10
2016-05-23	Add dret.	Tim Newsome	2	-3/+2
2016-05-23	Implement single memory read access.	Tim Newsome	2	-24/+29
2016-05-23	Exceptions in Debug Mode, stay in Debug Mode.	Tim Newsome	2	-16/+28
2016-05-23	Have Debug memory kind of working again.	Tim Newsome	2	-14/+13
2016-05-23	Fix race using fence.	Tim Newsome	2	-21/+16
2016-05-23	Refactor how we track in-progress operations.	Tim Newsome	1	-0/+1
2016-05-23	processor_t unfriends gdbserver_t.	Tim Newsome	2	-2/+2
2016-05-23	Add debug_module bus device.	Tim Newsome	3	-15/+14
2016-05-23	ROM -> RAM -> ROM, waiting for debug int.	Tim Newsome	2	-2/+2
2016-05-23	Jump to the correct (temporary) Debug RAM address.	Tim Newsome	2	-6/+7
2016-05-23	Clean up how Debug ROM is included.	Tim Newsome	4	-0/+154
2016-05-23	Can jump to and execute Debug ROM.	Tim Newsome	4	-154/+0
2016-05-23	Check in compiled debug ROM.	Tim Newsome	2	-3/+24
2016-05-23	Add debug rom code.	Tim Newsome	3	-0/+133