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path: root/debug_rom/debug_rom.S
AgeCommit message (Expand)AuthorFilesLines
2022-07-30DSCRATCH is now called DSCRATCH0Tim Newsome1-4/+4
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-0/+4
2019-04-02Implement debug hasel support (#287)Tim Newsome1-2/+5
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur1-2/+2
2017-06-08`make clean && make` works again in debug_romTim Newsome1-1/+1
2017-04-18debug: Add fence and fence.i to ensure Debug RAM is ready.Megan Wachs1-22/+9
2017-04-17debug: Use more unique debug ROM namesMegan Wachs1-15/+19
2017-04-17debug: Use a more practical debug ROMMegan Wachs1-139/+68
2016-06-22Parameterize debug ROM contents on XLENAndrew Waterman1-5/+48
2016-06-22Remove fence.i from debug ROMAndrew Waterman1-1/+0
2016-06-09Fix 2 bugs in Debug ROM: (#52)Tim Newsome1-5/+7
2016-06-03DCSR cause was moved, bug debug ROM wasn't updatedTim Newsome1-2/+2
2016-06-01Move sethaltnot and cleardebint.Tim Newsome1-2/+2
2016-05-24New encoding.h for new CSR addresses.Tim Newsome1-1/+1
2016-05-24Move cleardebint, per spec.Tim Newsome1-1/+1
2016-05-23Change DCSR bits to match spec.Tim Newsome1-19/+11
2016-05-23Use fence.i in Debug ROM.Tim Newsome1-0/+1
2016-05-23Add dret.Tim Newsome1-2/+1
2016-05-23Implement single memory read access.Tim Newsome1-8/+12
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome1-1/+12
2016-05-23Have Debug memory kind of working again.Tim Newsome1-6/+5
2016-05-23Fix race using fence.Tim Newsome1-5/+1
2016-05-23Refactor how we track in-progress operations.Tim Newsome1-0/+1
2016-05-23processor_t unfriends gdbserver_t.Tim Newsome1-1/+1
2016-05-23Add debug_module bus device.Tim Newsome1-10/+9
2016-05-23ROM -> RAM -> ROM, waiting for debug int.Tim Newsome1-1/+1
2016-05-23Jump to the correct (temporary) Debug RAM address.Tim Newsome1-1/+2
2016-05-23Clean up how Debug ROM is included.Tim Newsome1-0/+105
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-105/+0
2016-05-23Add debug rom code.Tim Newsome1-0/+105