Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2022-11-15 | Use ACTION_DEBUG_MODE instead of 1itrigger-etrigger-cleanup | YenHaoChen | 1 | -1/+1 | |
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | |||||
2022-11-15 | Update riscv/triggers.cc | YenHaoChen | 1 | -1/+1 | |
Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | |||||
2022-11-15 | fix compilation error: unused parameter | YenHaoChen | 2 | -4/+4 | |
2022-11-15 | check itrigger/etrigger after taking trap | YenHaoChen | 1 | -1/+6 | |
2022-11-15 | add take_trigger_action() to processor.h/processor.cc | YenHaoChen | 3 | -12/+25 | |
2022-11-15 | update module_t | YenHaoChen | 2 | -31/+82 | |
2022-11-15 | add itrigger_t and etrigger_t | YenHaoChen | 2 | -1/+153 | |
2022-11-15 | update debug_defines.h | YenHaoChen | 1 | -892/+1432 | |
2022-11-15 | add disabled_trigger_t to triggers | YenHaoChen | 2 | -0/+27 | |
2022-11-15 | trigger_t: Protect destructor and memory_access_match() | Tim Newsome | 1 | -7/+3 | |
2022-11-15 | triggers: Move trigger_t.hit to mcontrol_t.hit | Tim Newsome | 1 | -2/+1 | |
2022-11-15 | triggers: Access action bit through get_action() | Tim Newsome | 2 | -2/+4 | |
2022-11-15 | triggers: rename chain | Tim Newsome | 2 | -8/+8 | |
chain() -> get_chain() chain_bit -> chain | |||||
2022-11-15 | triggers: Rename/move dmode | Tim Newsome | 2 | -5/+7 | |
dmode() -> get_dmode() trigger_t.dmode_bit -> mcontrol_t.dmode | |||||
2022-11-15 | triggers: rename store | Tim Newsome | 3 | -7/+7 | |
store() -> get_store() store_bit -> store | |||||
2022-11-15 | Triggers: rename load | Tim Newsome | 3 | -7/+7 | |
load() -> get_load() load_bit -> bit | |||||
2022-11-15 | Triggers rename execute | Tim Newsome | 3 | -8/+8 | |
execute() -> get_execute(), execute_bit -> execute | |||||
2022-11-15 | Move tdata2 from mcontrol_t into its own class. | YenHaoChen | 2 | -16/+22 | |
structuralize trigger's tdata CSRs for modularization | |||||
2022-10-20 | Merge pull request #1122 from riscv-software-src/more-mmu-simplification | Andrew Waterman | 71 | -219/+190 | |
Fix minor MMU bugs; clean up MMU some more | |||||
2022-10-20 | Merge pull request #1125 from riscv-software-src/cbo-fixes | Andrew Waterman | 2 | -6/+8 | |
Fix tval reporting for CBOs; constrain cache-block sizes to reasonable values | |||||
2022-10-20 | Use reg_t, not uint64_t, for address-like quantities | Andrew Waterman | 1 | -2/+2 | |
2022-10-20 | Fix tval reporting for CBOs | Andrew Waterman | 1 | -2/+1 | |
mmu_t::translate may raise exceptions and so must be called with the original virtual address for tval to be set correctly. | |||||
2022-10-20 | Set 16..4096-byte bound on cache-block size | Andrew Waterman | 1 | -2/+5 | |
16 B suffices to subsume all aligned accesses (including the Q extension). Spike does not actually rely on this property, but in some real systems, it is impractical to guarantee atomicity across cache lines. 4096 B suffices to prevent cache lines from spanning pages (which would require multiple TLB accesses). This one is a bug fix, since we were not performing multiple TLB accesses in this case. | |||||
2022-10-20 | move fucntion cto() from processor.h to arith.h | YenHaoChen | 3 | -9/+10 | |
Only triggers.cc uses the arithmetic function cto(). Instead of putting the cto() in processor.h, putting it in arith.h with other arithmetic functions, e.g., ctz() and clz(), makes more sense. | |||||
2022-10-19 | Template-ize stores | Andrew Waterman | 17 | -40/+30 | |
2022-10-19 | Template-ize loads | Andrew Waterman | 22 | -54/+38 | |
2022-10-19 | Template-ize AMOs | Andrew Waterman | 20 | -34/+29 | |
2022-10-19 | DRY in store-conditional instructions | Andrew Waterman | 3 | -12/+15 | |
2022-10-19 | Simplify check_load_reservation | Andrew Waterman | 1 | -2/+2 | |
Invoking refill_tlb to get the physical address is somewhat baroque, and not even helpful in practice, since successful SCs will fill the TLB anyway. | |||||
2022-10-19 | Template-ize hypervisor loads and stores | Andrew Waterman | 14 | -33/+28 | |
2022-10-19 | Remove require_alignment flag from loads | Andrew Waterman | 2 | -7/+7 | |
The last remaining use was LR, which we can identify through other means. | |||||
2022-10-19 | Fix imprecise exception on LR to MMIO space | Andrew Waterman | 4 | -17/+14 | |
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise. | |||||
2022-10-19 | Template-ize load_func macro | Andrew Waterman | 1 | -15/+20 | |
For now, preserve the macro for compatibility with existing uses. | |||||
2022-10-19 | Template-ize store_func macro | Andrew Waterman | 1 | -14/+18 | |
For now, preserve the macro for compatibility with existing uses. | |||||
2022-10-19 | No need to require_alignment for the load part of the AMO | Andrew Waterman | 1 | -1/+1 | |
The earlier call to store_slow_path will catch the misalignment. | |||||
2022-10-19 | Remove actually_store and require_alignment parameters from store_func macro | Andrew Waterman | 1 | -8/+6 | |
These are now only used by AMOs. Since AMOs are relatively uncommon, and since the slow path really isn't slow anymore, send them down the slow path to simplify the common case. | |||||
2022-10-19 | remove duplicate CMO item in README.md | Weiwei Li | 1 | -1/+0 | |
2022-10-19 | do memcpy only for actually_store in store_slow_path_intrapage | Weiwei Li | 1 | -2/+4 | |
2022-10-19 | Fix missing sentinel warning in dts.cc when using gnu++17 standard | Weiwei Li | 1 | -1/+1 | |
2022-10-19 | Fix forced linking when compiling headers | bluew | 1 | -1/+1 | |
2022-10-17 | fix clang build | Andrew Waterman | 1 | -1/+1 | |
2022-10-17 | Add command to display privilege level in interactive mode | Jerry Zhao | 4 | -0/+32 | |
2022-10-17 | Make PLIC/NS16550 coding style more conformant | Andrew Waterman | 3 | -84/+61 | |
2022-10-17 | Merge branch 'master' into plic_uart_v1plic_uart_v1 | Andrew Waterman | 229 | -6973/+8037 | |
2022-10-16 | Add interactive mode commands to read clint mtime/mtimecmp | Jerry Zhao | 3 | -0/+27 | |
2022-10-14 | Add dump memory command to interactive mode | Jerry Zhao | 4 | -0/+29 | |
2022-10-14 | Support command-line configuration of number of pmpregions | Jerry Zhao | 5 | -2/+10 | |
2022-10-14 | Merge pull request #1114 from riscv-software-src/data_optional | Scott Johnson | 4 | -21/+21 | |
In triggers, use optional<data> instead of {has_data, data} | |||||
2022-10-14 | In triggers, use optional<data> instead of {has_data, data} | Andrew Waterman | 4 | -16/+17 | |
2022-10-14 | Report error if an unsupported memory configuration is detected | Parshintsev Anatoly | 2 | -9/+18 | |