Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2024-06-30 | Support parsing procs fully from DTSdts_parsing | Jerry Zhao | 3 | -23/+81 | |
2024-06-30 | Move isa property to a field of processor_t, not sim_t | Jerry Zhao | 7 | -33/+33 | |
This incidentally makes it easier to support heterogeneous-hart configs in the future | |||||
2024-06-30 | Pass cfg into make_dts | Jerry Zhao | 3 | -18/+15 | |
2024-06-28 | Merge pull request #1714 from abejgonzalez/fix-interactive-insn | Jerry Zhao | 1 | -29/+30 | |
Fix insn interactive command (catch/print trap, use proper access func) | |||||
2024-06-28 | Merge pull request #1715 from abejgonzalez/fix-interactive-vregs | Jerry Zhao | 1 | -29/+34 | |
Don't print vregs in interactive mode if no V extension exists | |||||
2024-06-28 | Don't print vregs if no V exts | abejgonzalez | 1 | -29/+34 | |
2024-06-28 | Fix insn interactive command (catch/print trap, use proper access func) | abejgonzalez | 1 | -29/+30 | |
2024-06-26 | Merge pull request #1709 from abejgonzalez/add-insn-debug-mode-cmds | Andrew Waterman | 2 | -19/+57 | |
Add insn cmd to interactive debug mode | |||||
2024-06-26 | Add insn cmds to interactive debug mode | abejgonzalez | 2 | -19/+57 | |
2024-06-26 | Merge pull request #1711 from riscv-software-src/zfa-disasm | Andrew Waterman | 1 | -1/+105 | |
Add disassembly for Zfa extension | |||||
2024-06-26 | Expand default disassembly ISA | Andrew Waterman | 1 | -1/+2 | |
2024-06-26 | Add disassembly for Zfa extension | Andrew Waterman | 1 | -0/+103 | |
2024-06-26 | Merge pull request #1710 from riscv-software-src/fix_debug_ci | Jerry Zhao | 1 | -1/+1 | |
Fix riscv-tests commit for CI | |||||
2024-06-26 | Fix riscv-tests commit for CI | Jerry Zhao | 1 | -1/+1 | |
* https://github.com/riscv-software-src/riscv-tests/pull/567 was merged by squash accidentally, so the reference commit was lost | |||||
2024-06-22 | Merge pull request #1705 from rpsene/master | Jerry Zhao | 1 | -0/+1 | |
2024-06-22 | Fix: Add missing <stdexcept> header for std::logic_error | Rafael Sene | 1 | -0/+1 | |
- Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'. Signed-off-by: Rafael Sene <rafael@riscv.org> | |||||
2024-06-21 | Merge pull request #1701 from riscv-software-src/zvl_zve | Jerry Zhao | 15 | -119/+93 | |
Correctly determine vector capability from v/zve/zvl ISA strings, remove --varch | |||||
2024-06-21 | Merge pull request #1704 from riscv-software-src/thread-local-again | Andrew Waterman | 1 | -2/+1 | |
Fix C/C++ thread-local linkage differently | |||||
2024-06-21 | Fix C/C++ thread-local linkage differently | Andrew Waterman | 1 | -2/+1 | |
Just admit Mac OS is broken, so explicitly special-case it. See #1689 and #1703 | |||||
2024-06-21 | Vector-fp instructions depend on zve, not F/D | Jerry Zhao | 2 | -10/+12 | |
2024-06-21 | Restrict spike to vlen <= 4096 | Jerry Zhao | 1 | -0/+4 | |
2024-06-21 | Remove all --varch parsing | Jerry Zhao | 9 | -93/+1 | |
2024-06-21 | Switch to Zvl/Zve parsing from isa_parser, instead of varch | Jerry Zhao | 1 | -1/+4 | |
2024-06-21 | Disallow any vector, not just V, when no __int128 type is present | Jerry Zhao | 1 | -1/+1 | |
2024-06-21 | Relax require_vector check for misa.V | Jerry Zhao | 1 | -2/+0 | |
2024-06-21 | Relax mstatus.vs dependency on full V | Jerry Zhao | 2 | -1/+5 | |
2024-06-21 | Relax vector_csr dependency on 'V' | Jerry Zhao | 1 | -4/+0 | |
2024-06-21 | Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve | Jerry Zhao | 1 | -3/+0 | |
2024-06-21 | Allow disassembly from implementations that are not full V | Jerry Zhao | 1 | -1/+1 | |
2024-06-21 | Relax has_fs dependency on misa.v | Jerry Zhao | 1 | -2/+1 | |
isa_parser should already require any Zvef or Zved extensions imply F/D | |||||
2024-06-21 | Add accessors to isa_parser's VLEN/ELEN | Jerry Zhao | 1 | -0/+3 | |
2024-06-21 | Add Zvl/Zve validation to isa_parser | Jerry Zhao | 1 | -0/+21 | |
2024-06-21 | Add isa_parser parsing for zvl/zve | Jerry Zhao | 2 | -1/+40 | |
2024-06-20 | Merge pull request #1702 from riscv-software-src/fix-1696 | Andrew Waterman | 1 | -20/+20 | |
In isa_parser, move extensionology code before error-checking code | |||||
2024-06-20 | In isa_parser, move extensionology code before error-checking code | Andrew Waterman | 1 | -20/+20 | |
Resolves #1696 | |||||
2024-06-20 | Merge pull request #1695 from riscv-software-src/bf16-ops | Andrew Waterman | 10 | -4/+443 | |
Add several BF16 ops to SoftFloat | |||||
2024-06-20 | Merge pull request #1690 from riscv-software-src/fix-warnings | Jerry Zhao | 2 | -17/+17 | |
Fix a few compile warnings | |||||
2024-06-18 | Add several BF16 ops to SoftFloat | Andrew Waterman | 10 | -0/+435 | |
2024-06-17 | Merge pull request #1694 from Du-Chao/master | Andrew Waterman | 1 | -1/+1 | |
Add a prerequisite for building | |||||
2024-06-18 | Add a prerequisite for building | Chao Du | 1 | -1/+1 | |
Otherwise, configure will fail with 'Could not find a version of the Boost::Asio library!' | |||||
2024-06-17 | Consistently order BF16 routines in Makefile and softfloat.h | Andrew Waterman | 2 | -4/+8 | |
2024-06-13 | Merge pull request #1689 from riscv-software-src/rounding-mode-thread-local | Andrew Waterman | 1 | -2/+5 | |
Make softfloat's rounding mode thread-local | |||||
2024-06-13 | Make softfloat's rounding mode thread-local | Andrew Waterman | 1 | -2/+5 | |
This has no effect on Spike itself, but it might matter for anyone who's using Spike as a library in a multithreaded program. | |||||
2024-06-13 | Merge branch 'NXP-zilsd' | Andrew Waterman | 11 | -17/+83 | |
2024-06-13 | Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32) | Christian Herber | 11 | -17/+83 | |
2024-06-12 | Fix a few compile warnings | Andrew Waterman | 2 | -17/+17 | |
2024-06-11 | Merge pull request #1679 from akifejaz/vector-crypto | Andrew Waterman | 1 | -0/+10 | |
Updated README with supported Vector Cryptography Extensions | |||||
2024-06-12 | Merge branch 'master' into vector-crypto | Akif Ejaz | 20 | -139/+199 | |
2024-06-11 | Merge pull request #1687 from riscv-software-src/flw-overlap | Andrew Waterman | 13 | -124/+179 | |
Separate RV32 and RV64 C instructions into separate files | |||||
2024-06-11 | Validate contents of overlap list in CI | Andrew Waterman | 1 | -13/+32 | |