diff options
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/execute.cc | 10 | ||||
-rw-r--r-- | riscv/insns/dret.h | 1 | ||||
-rw-r--r-- | riscv/insns/mnret.h | 1 | ||||
-rw-r--r-- | riscv/insns/mret.h | 1 | ||||
-rw-r--r-- | riscv/insns/sret.h | 1 | ||||
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/processor.h | 2 |
7 files changed, 12 insertions, 6 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 0751476..69dbd7d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -14,12 +14,12 @@ static void commit_log_reset(processor_t* p) p->get_state()->log_mem_write.clear(); } -static void stash_privilege(processor_t* p) +void processor_t::stash_privilege() { - state_t* state = p->get_state(); + state_t* state = get_state(); state->last_inst_priv = state->prv; - state->last_inst_xlen = p->get_xlen(); - state->last_inst_flen = p->get_flen(); + state->last_inst_xlen = get_xlen(); + state->last_inst_flen = get_flen(); state->last_v = state->v; } @@ -161,7 +161,6 @@ inline void processor_t::update_histogram(reg_t pc) // These two functions are expected to be inlined by the compiler separately in // the processor_t::step() loop. The logged variant is used in the slow path static inline reg_t execute_insn_fast(processor_t* p, reg_t pc, insn_fetch_t fetch) { - stash_privilege(p); return fetch.func(p, fetch.insn, pc); } static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t fetch) @@ -169,7 +168,6 @@ static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t f if (p->get_log_commits_enabled()) { commit_log_reset(p); } - stash_privilege(p); reg_t npc; diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 56ce25b..ffbe0ae 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,4 +1,5 @@ require(STATE.debug_mode); +p->stash_privilege(); set_pc_and_serialize(STATE.dpc->read()); p->set_privilege(STATE.dcsr->prv); if (STATE.prv < PRV_M) diff --git a/riscv/insns/mnret.h b/riscv/insns/mnret.h index bc69510..2888f8d 100644 --- a/riscv/insns/mnret.h +++ b/riscv/insns/mnret.h @@ -1,5 +1,6 @@ require_extension(EXT_SMRNMI); require_privilege(PRV_M); +p->stash_privilege(); set_pc_and_serialize(p->get_state()->mnepc->read()); reg_t s = STATE.mnstatus->read(); reg_t prev_prv = get_field(s, MNSTATUS_MNPP); diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 5198b8f..6cb6a0d 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -1,4 +1,5 @@ require_privilege(PRV_M); +p->stash_privilege(); set_pc_and_serialize(p->get_state()->mepc->read()); reg_t s = STATE.mstatus->read(); reg_t prev_prv = get_field(s, MSTATUS_MPP); diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index 5102c15..17e583d 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -1,4 +1,5 @@ require_extension('S'); +p->stash_privilege(); reg_t prev_hstatus = STATE.hstatus->read(); if (STATE.v) { if (STATE.prv == PRV_U || get_field(prev_hstatus, HSTATUS_VTSR)) diff --git a/riscv/processor.cc b/riscv/processor.cc index 984b9e5..f7cc5fe 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -783,6 +783,8 @@ void processor_t::debug_output_log(std::stringstream *s) void processor_t::take_trap(trap_t& t, reg_t epc) { + stash_privilege(); + unsigned max_xlen = isa->get_max_xlen(); if (debug) { diff --git a/riscv/processor.h b/riscv/processor.h index 914bd45..e37ff8b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -298,6 +298,8 @@ public: void clear_waiting_for_interrupt() { in_wfi = false; }; bool is_waiting_for_interrupt() { return in_wfi; }; + void stash_privilege(); + private: const isa_parser_t * const isa; const cfg_t * const cfg; |