diff options
Diffstat (limited to 'riscv/insns')
272 files changed, 811 insertions, 0 deletions
diff --git a/riscv/insns/add.h b/riscv/insns/add.h new file mode 100644 index 0000000..34d49ff --- /dev/null +++ b/riscv/insns/add.h @@ -0,0 +1 @@ +RD = sext_xprlen(RS1 + RS2); diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h new file mode 100644 index 0000000..88881e5 --- /dev/null +++ b/riscv/insns/addi.h @@ -0,0 +1 @@ +RD = sext_xprlen(RS1 + SIMM); diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h new file mode 100644 index 0000000..23ae278 --- /dev/null +++ b/riscv/insns/addiw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(SIMM + RS1); diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h new file mode 100644 index 0000000..4e2ed56 --- /dev/null +++ b/riscv/insns/addw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(RS1 + RS2); diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h new file mode 100644 index 0000000..b8450bf --- /dev/null +++ b/riscv/insns/amoadd_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 + v); +RD = v; diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h new file mode 100644 index 0000000..033b3c8 --- /dev/null +++ b/riscv/insns/amoadd_w.h @@ -0,0 +1,3 @@ +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 + v); +RD = v; diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h new file mode 100644 index 0000000..586eb7f --- /dev/null +++ b/riscv/insns/amoand_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 & v); +RD = v; diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h new file mode 100644 index 0000000..18a9249 --- /dev/null +++ b/riscv/insns/amoand_w.h @@ -0,0 +1,3 @@ +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 & v); +RD = v; diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h new file mode 100644 index 0000000..1a0bc8a --- /dev/null +++ b/riscv/insns/amomax_d.h @@ -0,0 +1,4 @@ +require_xpr64; +sreg_t v = mmu.load_int64(RS1); +mmu.store_uint64(RS1, std::max(sreg_t(RS2),v)); +RD = v; diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h new file mode 100644 index 0000000..ff9c2da --- /dev/null +++ b/riscv/insns/amomax_w.h @@ -0,0 +1,3 @@ +int32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::max(int32_t(RS2),v)); +RD = v; diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h new file mode 100644 index 0000000..ccfaf1d --- /dev/null +++ b/riscv/insns/amomaxu_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, std::max(RS2,v)); +RD = v; diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h new file mode 100644 index 0000000..075847d --- /dev/null +++ b/riscv/insns/amomaxu_w.h @@ -0,0 +1,3 @@ +uint32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::max(uint32_t(RS2),v)); +RD = (int32_t)v; diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h new file mode 100644 index 0000000..4f3b6d6 --- /dev/null +++ b/riscv/insns/amomin_d.h @@ -0,0 +1,4 @@ +require_xpr64; +sreg_t v = mmu.load_int64(RS1); +mmu.store_uint64(RS1, std::min(sreg_t(RS2),v)); +RD = v; diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h new file mode 100644 index 0000000..529ad50 --- /dev/null +++ b/riscv/insns/amomin_w.h @@ -0,0 +1,3 @@ +int32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::min(int32_t(RS2),v)); +RD = v; diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h new file mode 100644 index 0000000..c09c51a --- /dev/null +++ b/riscv/insns/amominu_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, std::min(RS2,v)); +RD = v; diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h new file mode 100644 index 0000000..d8d6377 --- /dev/null +++ b/riscv/insns/amominu_w.h @@ -0,0 +1,3 @@ +uint32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::min(uint32_t(RS2),v)); +RD = (int32_t)v; diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h new file mode 100644 index 0000000..76a4508 --- /dev/null +++ b/riscv/insns/amoor_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 | v); +RD = v; diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h new file mode 100644 index 0000000..741fbef --- /dev/null +++ b/riscv/insns/amoor_w.h @@ -0,0 +1,3 @@ +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 | v); +RD = v; diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h new file mode 100644 index 0000000..43e3538 --- /dev/null +++ b/riscv/insns/amoswap_d.h @@ -0,0 +1,4 @@ +require_xpr64; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2); +RD = v; diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h new file mode 100644 index 0000000..30e6102 --- /dev/null +++ b/riscv/insns/amoswap_w.h @@ -0,0 +1,3 @@ +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2); +RD = v; diff --git a/riscv/insns/and.h b/riscv/insns/and.h new file mode 100644 index 0000000..88ac1d8 --- /dev/null +++ b/riscv/insns/and.h @@ -0,0 +1 @@ +RD = RS1 & RS2; diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h new file mode 100644 index 0000000..5caea16 --- /dev/null +++ b/riscv/insns/andi.h @@ -0,0 +1 @@ +RD = SIMM & RS1; diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h new file mode 100644 index 0000000..7b26488 --- /dev/null +++ b/riscv/insns/beq.h @@ -0,0 +1,2 @@ +if(cmp_trunc(RS1) == cmp_trunc(RS2)) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h new file mode 100644 index 0000000..dca544b --- /dev/null +++ b/riscv/insns/bge.h @@ -0,0 +1,2 @@ +if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2))) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h new file mode 100644 index 0000000..6325466 --- /dev/null +++ b/riscv/insns/bgeu.h @@ -0,0 +1,2 @@ +if(cmp_trunc(RS1) >= cmp_trunc(RS2)) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h new file mode 100644 index 0000000..d84fd7a --- /dev/null +++ b/riscv/insns/blt.h @@ -0,0 +1,2 @@ +if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2))) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h new file mode 100644 index 0000000..250fd4f --- /dev/null +++ b/riscv/insns/bltu.h @@ -0,0 +1,2 @@ +if(cmp_trunc(RS1) < cmp_trunc(RS2)) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h new file mode 100644 index 0000000..f775721 --- /dev/null +++ b/riscv/insns/bne.h @@ -0,0 +1,2 @@ +if(cmp_trunc(RS1) != cmp_trunc(RS2)) + set_pc(BRANCH_TARGET); diff --git a/riscv/insns/break.h b/riscv/insns/break.h new file mode 100644 index 0000000..7fd3d66 --- /dev/null +++ b/riscv/insns/break.h @@ -0,0 +1 @@ +throw trap_breakpoint; diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h new file mode 100644 index 0000000..2170d69 --- /dev/null +++ b/riscv/insns/c_add.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = CRS1 + CRS2; diff --git a/riscv/insns/c_add3.h b/riscv/insns/c_add3.h new file mode 100644 index 0000000..914c85d --- /dev/null +++ b/riscv/insns/c_add3.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = CRS1S + CRS2BS; diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h new file mode 100644 index 0000000..448e31a --- /dev/null +++ b/riscv/insns/c_addi.h @@ -0,0 +1,10 @@ +require_rvc; +if(CRD_REGNUM == 0) +{ + reg_t temp = CRS1; + if(CIMM6 & 0x20) + RA = npc; + set_pc(temp); +} +else + CRD = sext_xprlen(CRS2 + CIMM6); diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h new file mode 100644 index 0000000..6a1e0a3 --- /dev/null +++ b/riscv/insns/c_addiw.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRD = sext32(CRS2 + CIMM6); diff --git a/riscv/insns/c_and3.h b/riscv/insns/c_and3.h new file mode 100644 index 0000000..b506d6a --- /dev/null +++ b/riscv/insns/c_and3.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = CRS1S & CRS2BS; diff --git a/riscv/insns/c_beq.h b/riscv/insns/c_beq.h new file mode 100644 index 0000000..031d96d --- /dev/null +++ b/riscv/insns/c_beq.h @@ -0,0 +1,3 @@ +require_rvc; +if(cmp_trunc(CRS1S) == cmp_trunc(CRS2S)) + set_pc(CBRANCH_TARGET); diff --git a/riscv/insns/c_bne.h b/riscv/insns/c_bne.h new file mode 100644 index 0000000..caf9229 --- /dev/null +++ b/riscv/insns/c_bne.h @@ -0,0 +1,3 @@ +require_rvc; +if(cmp_trunc(CRS1S) != cmp_trunc(CRS2S)) + set_pc(CBRANCH_TARGET); diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h new file mode 100644 index 0000000..a726039 --- /dev/null +++ b/riscv/insns/c_fld.h @@ -0,0 +1,3 @@ +require_rvc; +require_fp; +FCRDS = mmu.load_int64(CRS1S+CIMM5*8); diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h new file mode 100644 index 0000000..cdb7221 --- /dev/null +++ b/riscv/insns/c_flw.h @@ -0,0 +1,3 @@ +require_rvc; +require_fp; +FCRDS = mmu.load_int32(CRS1S+CIMM5*4); diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h new file mode 100644 index 0000000..20814fd --- /dev/null +++ b/riscv/insns/c_fsd.h @@ -0,0 +1,3 @@ +require_rvc; +require_fp; +mmu.store_uint64(CRS1S+CIMM5*8, FCRS2S); diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h new file mode 100644 index 0000000..1d21629 --- /dev/null +++ b/riscv/insns/c_fsw.h @@ -0,0 +1,3 @@ +require_rvc; +require_fp; +mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S); diff --git a/riscv/insns/c_j.h b/riscv/insns/c_j.h new file mode 100644 index 0000000..5ba9c73 --- /dev/null +++ b/riscv/insns/c_j.h @@ -0,0 +1,2 @@ +require_rvc; +set_pc(CJUMP_TARGET); diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h new file mode 100644 index 0000000..f9c07af --- /dev/null +++ b/riscv/insns/c_ld.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = mmu.load_int64(CRS1S+CIMM5*8); diff --git a/riscv/insns/c_ld0.h b/riscv/insns/c_ld0.h new file mode 100644 index 0000000..f51a966 --- /dev/null +++ b/riscv/insns/c_ld0.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRD = mmu.load_int64(CRS1); diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h new file mode 100644 index 0000000..1fbd9bd --- /dev/null +++ b/riscv/insns/c_ldsp.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRD = mmu.load_int64(XPR[30]+CIMM6*8); diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h new file mode 100644 index 0000000..e65614e --- /dev/null +++ b/riscv/insns/c_li.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = CIMM6; diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h new file mode 100644 index 0000000..4796ab8 --- /dev/null +++ b/riscv/insns/c_lw.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = mmu.load_int32(CRS1S+CIMM5*4); diff --git a/riscv/insns/c_lw0.h b/riscv/insns/c_lw0.h new file mode 100644 index 0000000..d263a80 --- /dev/null +++ b/riscv/insns/c_lw0.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = mmu.load_int32(CRS1); diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h new file mode 100644 index 0000000..318342a --- /dev/null +++ b/riscv/insns/c_lwsp.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = mmu.load_int32(XPR[30]+CIMM6*4); diff --git a/riscv/insns/c_move.h b/riscv/insns/c_move.h new file mode 100644 index 0000000..b0aef33 --- /dev/null +++ b/riscv/insns/c_move.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = CRS1; diff --git a/riscv/insns/c_or3.h b/riscv/insns/c_or3.h new file mode 100644 index 0000000..143e2ae --- /dev/null +++ b/riscv/insns/c_or3.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = CRS1S | CRS2BS; diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h new file mode 100644 index 0000000..b2eb456 --- /dev/null +++ b/riscv/insns/c_sd.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +mmu.store_uint64(CRS1S+CIMM5*8, CRS2S); diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h new file mode 100644 index 0000000..ca97d51 --- /dev/null +++ b/riscv/insns/c_sdsp.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +mmu.store_uint64(XPR[30]+CIMM6*8, CRS2); diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h new file mode 100644 index 0000000..5026767 --- /dev/null +++ b/riscv/insns/c_slli.h @@ -0,0 +1,5 @@ +require_rvc; +if(xpr64) + CRDS = CRDS << CIMM5U; +else + CRDS = sext32(CRDS << CIMM5U); diff --git a/riscv/insns/c_slli32.h b/riscv/insns/c_slli32.h new file mode 100644 index 0000000..1e3e958 --- /dev/null +++ b/riscv/insns/c_slli32.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = CRDS << (32+CIMM5U); diff --git a/riscv/insns/c_slliw.h b/riscv/insns/c_slliw.h new file mode 100644 index 0000000..9e428f5 --- /dev/null +++ b/riscv/insns/c_slliw.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = sext32(CRDS << CIMM5U); diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h new file mode 100644 index 0000000..aa33424 --- /dev/null +++ b/riscv/insns/c_srai.h @@ -0,0 +1,5 @@ +require_rvc; +if(xpr64) + CRDS = sreg_t(CRDS) >> CIMM5U; +else + CRDS = sext32(int32_t(CRDS) >> CIMM5U); diff --git a/riscv/insns/c_srai32.h b/riscv/insns/c_srai32.h new file mode 100644 index 0000000..ca7b024 --- /dev/null +++ b/riscv/insns/c_srai32.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = sreg_t(CRDS) >> (32+CIMM5U); diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h new file mode 100644 index 0000000..56e0681 --- /dev/null +++ b/riscv/insns/c_srli.h @@ -0,0 +1,5 @@ +require_rvc; +if(xpr64) + CRDS = CRDS >> CIMM5U; +else + CRDS = sext32(uint32_t(CRDS) >> CIMM5U); diff --git a/riscv/insns/c_srli32.h b/riscv/insns/c_srli32.h new file mode 100644 index 0000000..4f5b8ea --- /dev/null +++ b/riscv/insns/c_srli32.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = CRDS >> (32+CIMM5U); diff --git a/riscv/insns/c_sub.h b/riscv/insns/c_sub.h new file mode 100644 index 0000000..9fd8932 --- /dev/null +++ b/riscv/insns/c_sub.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = CRS1 - CRS2; diff --git a/riscv/insns/c_sub3.h b/riscv/insns/c_sub3.h new file mode 100644 index 0000000..53afc84 --- /dev/null +++ b/riscv/insns/c_sub3.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = CRS1S - CRS2BS; diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h new file mode 100644 index 0000000..f604adf --- /dev/null +++ b/riscv/insns/c_sw.h @@ -0,0 +1,2 @@ +require_rvc; +mmu.store_uint32(CRS1S+CIMM5*4, CRS2S); diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h new file mode 100644 index 0000000..0508f12 --- /dev/null +++ b/riscv/insns/c_swsp.h @@ -0,0 +1,2 @@ +require_rvc; +mmu.store_uint32(XPR[30]+CIMM6*4, CRS2); diff --git a/riscv/insns/cflush.h b/riscv/insns/cflush.h new file mode 100644 index 0000000..5117ca0 --- /dev/null +++ b/riscv/insns/cflush.h @@ -0,0 +1 @@ +require_supervisor; diff --git a/riscv/insns/di.h b/riscv/insns/di.h new file mode 100644 index 0000000..31280d5 --- /dev/null +++ b/riscv/insns/di.h @@ -0,0 +1,4 @@ +require_supervisor; +uint32_t temp = sr; +set_sr(sr & ~SR_ET); +RD = temp; diff --git a/riscv/insns/div.h b/riscv/insns/div.h new file mode 100644 index 0000000..82a4066 --- /dev/null +++ b/riscv/insns/div.h @@ -0,0 +1,6 @@ +if(RS2 == 0) + RD = UINT64_MAX; +else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) + RD = RS1; +else + RD = sext_xprlen(sext_xprlen(RS1) / sext_xprlen(RS2)); diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h new file mode 100644 index 0000000..681afd2 --- /dev/null +++ b/riscv/insns/divu.h @@ -0,0 +1,4 @@ +if(RS2 == 0) + RD = UINT64_MAX; +else + RD = sext_xprlen(zext_xprlen(RS1) / zext_xprlen(RS2)); diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h new file mode 100644 index 0000000..0ceb040 --- /dev/null +++ b/riscv/insns/divuw.h @@ -0,0 +1,5 @@ +require_xpr64; +if(RS2 == 0) + RD = UINT64_MAX; +else + RD = sext32(zext32(RS1) / zext32(RS2)); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h new file mode 100644 index 0000000..51c3d80 --- /dev/null +++ b/riscv/insns/divw.h @@ -0,0 +1,7 @@ +require_xpr64; +if(RS2 == 0) + RD = UINT64_MAX; +else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) + RD = RS1; +else + RD = sext32(int32_t(RS1) / int32_t(RS2)); diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h new file mode 100644 index 0000000..8306aeb --- /dev/null +++ b/riscv/insns/ei.h @@ -0,0 +1,4 @@ +require_supervisor; +uint32_t temp = sr; +set_sr(sr | SR_ET); +RD = temp; diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h new file mode 100644 index 0000000..46d5bed --- /dev/null +++ b/riscv/insns/eret.h @@ -0,0 +1,5 @@ +require_supervisor; +if(sr & SR_ET) + throw trap_illegal_instruction; +set_sr(((sr & SR_PS) ? sr : (sr & ~SR_S)) | SR_ET); +set_pc(epc); diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h new file mode 100644 index 0000000..48c76a7 --- /dev/null +++ b/riscv/insns/fadd_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_add(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h new file mode 100644 index 0000000..2fd5429 --- /dev/null +++ b/riscv/insns/fadd_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_add(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h new file mode 100644 index 0000000..68c0482 --- /dev/null +++ b/riscv/insns/fcvt_d_l.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +FRD = i64_to_f64(RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h new file mode 100644 index 0000000..2032758 --- /dev/null +++ b/riscv/insns/fcvt_d_lu.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +FRD = ui64_to_f64(RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h new file mode 100644 index 0000000..6b1a09c --- /dev/null +++ b/riscv/insns/fcvt_d_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_to_f64(FRS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h new file mode 100644 index 0000000..52abd75 --- /dev/null +++ b/riscv/insns/fcvt_d_w.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = i32_to_f64((int32_t)RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h new file mode 100644 index 0000000..61a8a78 --- /dev/null +++ b/riscv/insns/fcvt_d_wu.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = ui32_to_f64((uint32_t)RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h new file mode 100644 index 0000000..206ba4f --- /dev/null +++ b/riscv/insns/fcvt_l_d.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +RD = f64_to_i64(FRS1, RM, true); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h new file mode 100644 index 0000000..e05f476 --- /dev/null +++ b/riscv/insns/fcvt_l_s.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +RD = f32_to_i64(FRS1, RM, true); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h new file mode 100644 index 0000000..44c3dd6 --- /dev/null +++ b/riscv/insns/fcvt_lu_d.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +RD = f64_to_ui64(FRS1, RM, true); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h new file mode 100644 index 0000000..13de436 --- /dev/null +++ b/riscv/insns/fcvt_lu_s.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +RD = f32_to_ui64(FRS1, RM, true); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h new file mode 100644 index 0000000..e5289c4 --- /dev/null +++ b/riscv/insns/fcvt_s_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_to_f32(FRS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h new file mode 100644 index 0000000..f149229 --- /dev/null +++ b/riscv/insns/fcvt_s_l.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +FRD = i64_to_f32(RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h new file mode 100644 index 0000000..d9d0946 --- /dev/null +++ b/riscv/insns/fcvt_s_lu.h @@ -0,0 +1,5 @@ +require_xpr64; +require_fp; +softfloat_roundingMode = RM; +FRD = ui64_to_f32(RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h new file mode 100644 index 0000000..dedebb5 --- /dev/null +++ b/riscv/insns/fcvt_s_w.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = i32_to_f32((int32_t)RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h new file mode 100644 index 0000000..abb782c --- /dev/null +++ b/riscv/insns/fcvt_s_wu.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = ui32_to_f32((uint32_t)RS1); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h new file mode 100644 index 0000000..88dc3d3 --- /dev/null +++ b/riscv/insns/fcvt_w_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +RD = sext32(f64_to_i32(FRS1, RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h new file mode 100644 index 0000000..f14cc19 --- /dev/null +++ b/riscv/insns/fcvt_w_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +RD = sext32(f32_to_i32(FRS1, RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h new file mode 100644 index 0000000..43ad6f6 --- /dev/null +++ b/riscv/insns/fcvt_wu_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +RD = sext32(f64_to_ui32(FRS1, RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h new file mode 100644 index 0000000..ff7a11c --- /dev/null +++ b/riscv/insns/fcvt_wu_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +RD = sext32(f32_to_ui32(FRS1, RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h new file mode 100644 index 0000000..aa00c98 --- /dev/null +++ b/riscv/insns/fdiv_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_div(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h new file mode 100644 index 0000000..8c76587 --- /dev/null +++ b/riscv/insns/fdiv_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_div(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fence.h b/riscv/insns/fence.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/fence.h diff --git a/riscv/insns/fence_g_cv.h b/riscv/insns/fence_g_cv.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/fence_g_cv.h diff --git a/riscv/insns/fence_g_v.h b/riscv/insns/fence_g_v.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/fence_g_v.h diff --git a/riscv/insns/fence_i.h b/riscv/insns/fence_i.h new file mode 100644 index 0000000..a2dbffe --- /dev/null +++ b/riscv/insns/fence_i.h @@ -0,0 +1 @@ +mmu.flush_icache(); diff --git a/riscv/insns/fence_l_cv.h b/riscv/insns/fence_l_cv.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/fence_l_cv.h diff --git a/riscv/insns/fence_l_v.h b/riscv/insns/fence_l_v.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/fence_l_v.h diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h new file mode 100644 index 0000000..9db8760 --- /dev/null +++ b/riscv/insns/feq_d.h @@ -0,0 +1,3 @@ +require_fp; +RD = f64_eq(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h new file mode 100644 index 0000000..658e8f6 --- /dev/null +++ b/riscv/insns/feq_s.h @@ -0,0 +1,3 @@ +require_fp; +RD = f32_eq(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h new file mode 100644 index 0000000..123dea4 --- /dev/null +++ b/riscv/insns/fld.h @@ -0,0 +1,2 @@ +require_fp; +FRD = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h new file mode 100644 index 0000000..da76187 --- /dev/null +++ b/riscv/insns/fle_d.h @@ -0,0 +1,3 @@ +require_fp; +RD = f64_le(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h new file mode 100644 index 0000000..9c83a17 --- /dev/null +++ b/riscv/insns/fle_s.h @@ -0,0 +1,3 @@ +require_fp; +RD = f32_le(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h new file mode 100644 index 0000000..01d135a --- /dev/null +++ b/riscv/insns/flt_d.h @@ -0,0 +1,3 @@ +require_fp; +RD = f64_lt(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h new file mode 100644 index 0000000..52eee5d --- /dev/null +++ b/riscv/insns/flt_s.h @@ -0,0 +1,3 @@ +require_fp; +RD = f32_lt(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h new file mode 100644 index 0000000..335fd7d --- /dev/null +++ b/riscv/insns/flw.h @@ -0,0 +1,2 @@ +require_fp; +FRD = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h new file mode 100644 index 0000000..f67853e --- /dev/null +++ b/riscv/insns/fmadd_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_mulAdd(FRS1, FRS2, FRS3); +set_fp_exceptions; diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h new file mode 100644 index 0000000..19db642 --- /dev/null +++ b/riscv/insns/fmadd_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_mulAdd(FRS1, FRS2, FRS3); +set_fp_exceptions; diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h new file mode 100644 index 0000000..cbbb343 --- /dev/null +++ b/riscv/insns/fmax_d.h @@ -0,0 +1,4 @@ +require_fp; +FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ + ? FRS1 : FRS2; +set_fp_exceptions; diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h new file mode 100644 index 0000000..8df665f --- /dev/null +++ b/riscv/insns/fmax_s.h @@ -0,0 +1,4 @@ +require_fp; +FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */ + ? FRS1 : FRS2; +set_fp_exceptions; diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h new file mode 100644 index 0000000..3d3d454 --- /dev/null +++ b/riscv/insns/fmin_d.h @@ -0,0 +1,4 @@ +require_fp; +FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ + ? FRS1 : FRS2; +set_fp_exceptions; diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h new file mode 100644 index 0000000..994c860 --- /dev/null +++ b/riscv/insns/fmin_s.h @@ -0,0 +1,4 @@ +require_fp; +FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */ + ? FRS1 : FRS2; +set_fp_exceptions; diff --git a/riscv/insns/fmovn.h b/riscv/insns/fmovn.h new file mode 100644 index 0000000..394b56c --- /dev/null +++ b/riscv/insns/fmovn.h @@ -0,0 +1,2 @@ +require_vector; +if (RS1 & 0x1) FRD = FRS2; diff --git a/riscv/insns/fmovz.h b/riscv/insns/fmovz.h new file mode 100644 index 0000000..7862216 --- /dev/null +++ b/riscv/insns/fmovz.h @@ -0,0 +1,2 @@ +require_vector; +if (~RS1 & 0x1) FRD = FRS2; diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h new file mode 100644 index 0000000..b1e9340 --- /dev/null +++ b/riscv/insns/fmsub_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN); +set_fp_exceptions; diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h new file mode 100644 index 0000000..d3349f5 --- /dev/null +++ b/riscv/insns/fmsub_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN); +set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h new file mode 100644 index 0000000..a8adedd --- /dev/null +++ b/riscv/insns/fmul_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_mul(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h new file mode 100644 index 0000000..6475578 --- /dev/null +++ b/riscv/insns/fmul_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_mul(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h new file mode 100644 index 0000000..1e2ee27 --- /dev/null +++ b/riscv/insns/fnmadd_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN; +set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h new file mode 100644 index 0000000..78abb78 --- /dev/null +++ b/riscv/insns/fnmadd_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN; +set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h new file mode 100644 index 0000000..ae643a5 --- /dev/null +++ b/riscv/insns/fnmsub_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; +set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h new file mode 100644 index 0000000..cbb70ba --- /dev/null +++ b/riscv/insns/fnmsub_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; +set_fp_exceptions; diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h new file mode 100644 index 0000000..113398e --- /dev/null +++ b/riscv/insns/fsd.h @@ -0,0 +1,2 @@ +require_fp; +mmu.store_uint64(RS1+BIMM, FRS2); diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h new file mode 100644 index 0000000..f66e804 --- /dev/null +++ b/riscv/insns/fsgnj_d.h @@ -0,0 +1,2 @@ +require_fp; +FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN); diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h new file mode 100644 index 0000000..35609ac --- /dev/null +++ b/riscv/insns/fsgnj_s.h @@ -0,0 +1,2 @@ +require_fp; +FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h new file mode 100644 index 0000000..22de215 --- /dev/null +++ b/riscv/insns/fsgnjn_d.h @@ -0,0 +1,2 @@ +require_fp; +FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN); diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h new file mode 100644 index 0000000..dd66d71 --- /dev/null +++ b/riscv/insns/fsgnjn_s.h @@ -0,0 +1,2 @@ +require_fp; +FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h new file mode 100644 index 0000000..331b6e4 --- /dev/null +++ b/riscv/insns/fsgnjx_d.h @@ -0,0 +1,2 @@ +require_fp; +FRD = FRS1 ^ (FRS2 & INT64_MIN); diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h new file mode 100644 index 0000000..b455406 --- /dev/null +++ b/riscv/insns/fsgnjx_s.h @@ -0,0 +1,2 @@ +require_fp; +FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h new file mode 100644 index 0000000..7647c9c --- /dev/null +++ b/riscv/insns/fsqrt_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_sqrt(FRS1); +set_fp_exceptions; diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h new file mode 100644 index 0000000..426f241 --- /dev/null +++ b/riscv/insns/fsqrt_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_sqrt(FRS1); +set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h new file mode 100644 index 0000000..e25eebb --- /dev/null +++ b/riscv/insns/fsub_d.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f64_sub(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h new file mode 100644 index 0000000..6c64d04 --- /dev/null +++ b/riscv/insns/fsub_s.h @@ -0,0 +1,4 @@ +require_fp; +softfloat_roundingMode = RM; +FRD = f32_sub(FRS1, FRS2); +set_fp_exceptions; diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h new file mode 100644 index 0000000..23d3333 --- /dev/null +++ b/riscv/insns/fsw.h @@ -0,0 +1,2 @@ +require_fp; +mmu.store_uint32(RS1+BIMM, FRS2); diff --git a/riscv/insns/j.h b/riscv/insns/j.h new file mode 100644 index 0000000..3a4da2a --- /dev/null +++ b/riscv/insns/j.h @@ -0,0 +1 @@ +set_pc(JUMP_TARGET); diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h new file mode 100644 index 0000000..41dc403 --- /dev/null +++ b/riscv/insns/jal.h @@ -0,0 +1,2 @@ +RA = npc; +set_pc(JUMP_TARGET); diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h new file mode 100644 index 0000000..91be911 --- /dev/null +++ b/riscv/insns/jalr_c.h @@ -0,0 +1,3 @@ +reg_t temp = RS1; +RD = npc; +set_pc(temp + SIMM); diff --git a/riscv/insns/jalr_j.h b/riscv/insns/jalr_j.h new file mode 100644 index 0000000..0d2ef12 --- /dev/null +++ b/riscv/insns/jalr_j.h @@ -0,0 +1 @@ +#include "insns/jalr_c.h" diff --git a/riscv/insns/jalr_r.h b/riscv/insns/jalr_r.h new file mode 100644 index 0000000..0d2ef12 --- /dev/null +++ b/riscv/insns/jalr_r.h @@ -0,0 +1 @@ +#include "insns/jalr_c.h" diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h new file mode 100644 index 0000000..81ba7de --- /dev/null +++ b/riscv/insns/lb.h @@ -0,0 +1 @@ +RD = mmu.load_int8(RS1+SIMM); diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h new file mode 100644 index 0000000..12c688a --- /dev/null +++ b/riscv/insns/lbu.h @@ -0,0 +1 @@ +RD = mmu.load_uint8(RS1+SIMM); diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h new file mode 100644 index 0000000..940d348 --- /dev/null +++ b/riscv/insns/ld.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h new file mode 100644 index 0000000..ec25bc4 --- /dev/null +++ b/riscv/insns/lh.h @@ -0,0 +1 @@ +RD = mmu.load_int16(RS1+SIMM); diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h new file mode 100644 index 0000000..0999c00 --- /dev/null +++ b/riscv/insns/lhu.h @@ -0,0 +1 @@ +RD = mmu.load_uint16(RS1+SIMM); diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h new file mode 100644 index 0000000..6af2a2a --- /dev/null +++ b/riscv/insns/lui.h @@ -0,0 +1 @@ +RD = sext32(BIGIMM << IMM_BITS); diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h new file mode 100644 index 0000000..769c9fd --- /dev/null +++ b/riscv/insns/lw.h @@ -0,0 +1 @@ +RD = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h new file mode 100644 index 0000000..f8f9841 --- /dev/null +++ b/riscv/insns/lwu.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = mmu.load_uint32(RS1+SIMM); diff --git a/riscv/insns/mffsr.h b/riscv/insns/mffsr.h new file mode 100644 index 0000000..29debc4 --- /dev/null +++ b/riscv/insns/mffsr.h @@ -0,0 +1,2 @@ +require_fp; +RD = fsr; diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h new file mode 100644 index 0000000..7de089e --- /dev/null +++ b/riscv/insns/mfpcr.h @@ -0,0 +1,68 @@ +require_supervisor; + +reg_t val; + +switch(insn.rtype.rs2) +{ + case 0: + val = sr; + break; + case 1: + val = epc; + break; + case 2: + val = badvaddr; + break; + case 3: + val = evec; + break; + case 4: + val = count; + break; + case 5: + val = compare; + break; + case 6: + val = cause; + break; + case 7: + val = 0; + cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT)); + break; + + case 8: + val = mmu.memsz >> PGSHIFT; + break; + + case 9: + val = mmu.get_ptbr(); + break; + + case 10: + val = id; + break; + + case 11: + val = vecbanks; + break; + + case 12: + val = sim.num_cores(); + break; + + case 17: + val = sim.get_fromhost(); + break; + + case 24: + val = pcr_k0; + break; + case 25: + val = pcr_k1; + break; + + default: + val = -1; +} + +RD = sext_xprlen(val); diff --git a/riscv/insns/mftx_d.h b/riscv/insns/mftx_d.h new file mode 100644 index 0000000..31be4cb --- /dev/null +++ b/riscv/insns/mftx_d.h @@ -0,0 +1,3 @@ +require_xpr64; +require_fp; +RD = FRS2; diff --git a/riscv/insns/mftx_s.h b/riscv/insns/mftx_s.h new file mode 100644 index 0000000..589b33b --- /dev/null +++ b/riscv/insns/mftx_s.h @@ -0,0 +1,2 @@ +require_fp; +RD = sext32(FRS2); diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h new file mode 100644 index 0000000..402d6d3 --- /dev/null +++ b/riscv/insns/movn.h @@ -0,0 +1,2 @@ +require_vector; +if (RS1 & 0x1) RD = RS2; diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h new file mode 100644 index 0000000..74cf8a9 --- /dev/null +++ b/riscv/insns/movz.h @@ -0,0 +1,2 @@ +require_vector; +if (~RS1 & 0x1) RD = RS2; diff --git a/riscv/insns/mtfsr.h b/riscv/insns/mtfsr.h new file mode 100644 index 0000000..cc6f9ea --- /dev/null +++ b/riscv/insns/mtfsr.h @@ -0,0 +1,4 @@ +require_fp; +uint32_t tmp = fsr; +set_fsr(RS1); +RD = tmp; diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h new file mode 100644 index 0000000..59f864f --- /dev/null +++ b/riscv/insns/mtpcr.h @@ -0,0 +1,45 @@ +require_supervisor; + +switch(insn.rtype.rs2) +{ + case 0: + set_sr(RS1); + break; + case 1: + epc = RS1; + break; + case 3: + evec = RS1; + break; + case 4: + count = RS1; + break; + case 5: + cause &= ~(1 << (TIMER_IRQ+CAUSE_IP_SHIFT)); + compare = RS1; + break; + + case 7: + sim.send_ipi(RS1); + break; + + case 9: + mmu.set_ptbr(RS1); + break; + + case 11: + vecbanks = RS1 & 0xff; + vecbanks_count = __builtin_popcountll(vecbanks); + break; + + case 16: + sim.set_tohost(RS1); + break; + + case 24: + pcr_k0 = RS1; + break; + case 25: + pcr_k1 = RS1; + break; +} diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h new file mode 100644 index 0000000..770d733 --- /dev/null +++ b/riscv/insns/mul.h @@ -0,0 +1 @@ +RD = sext_xprlen(RS1 * RS2); diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h new file mode 100644 index 0000000..f771a62 --- /dev/null +++ b/riscv/insns/mulh.h @@ -0,0 +1,8 @@ +if(xpr64) +{ + int64_t a = RS1; + int64_t b = RS2; + RD = (int128_t(a) * int128_t(b)) >> 64; +} +else + RD = sext32((sext32(RS1) * sext32(RS2)) >> 32); diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h new file mode 100644 index 0000000..c832657 --- /dev/null +++ b/riscv/insns/mulhsu.h @@ -0,0 +1,8 @@ +if(xpr64) +{ + int64_t a = RS1; + uint64_t b = RS2; + RD = (int128_t(a) * uint128_t(b)) >> 64; +} +else + RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32); diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h new file mode 100644 index 0000000..6334426 --- /dev/null +++ b/riscv/insns/mulhu.h @@ -0,0 +1,4 @@ +if(xpr64) + RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64; +else + RD = sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32); diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h new file mode 100644 index 0000000..7b0a934 --- /dev/null +++ b/riscv/insns/mulw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(RS1 * RS2); diff --git a/riscv/insns/mxtf_d.h b/riscv/insns/mxtf_d.h new file mode 100644 index 0000000..29792ec --- /dev/null +++ b/riscv/insns/mxtf_d.h @@ -0,0 +1,3 @@ +require_xpr64; +require_fp; +FRD = RS1; diff --git a/riscv/insns/mxtf_s.h b/riscv/insns/mxtf_s.h new file mode 100644 index 0000000..54546ea --- /dev/null +++ b/riscv/insns/mxtf_s.h @@ -0,0 +1,2 @@ +require_fp; +FRD = RS1; diff --git a/riscv/insns/or.h b/riscv/insns/or.h new file mode 100644 index 0000000..07bcac3 --- /dev/null +++ b/riscv/insns/or.h @@ -0,0 +1 @@ +RD = RS1 | RS2; diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h new file mode 100644 index 0000000..9561b97 --- /dev/null +++ b/riscv/insns/ori.h @@ -0,0 +1 @@ +RD = SIMM | RS1; diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h new file mode 100644 index 0000000..9b966a6 --- /dev/null +++ b/riscv/insns/rdcycle.h @@ -0,0 +1 @@ +RD = cycle; diff --git a/riscv/insns/rdinstret.h b/riscv/insns/rdinstret.h new file mode 100644 index 0000000..9b966a6 --- /dev/null +++ b/riscv/insns/rdinstret.h @@ -0,0 +1 @@ +RD = cycle; diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h new file mode 100644 index 0000000..5525421 --- /dev/null +++ b/riscv/insns/rdnpc.h @@ -0,0 +1 @@ +RD = npc; diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h new file mode 100644 index 0000000..9b966a6 --- /dev/null +++ b/riscv/insns/rdtime.h @@ -0,0 +1 @@ +RD = cycle; diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h new file mode 100644 index 0000000..ac82a56 --- /dev/null +++ b/riscv/insns/rem.h @@ -0,0 +1,6 @@ +if(RS2 == 0) + RD = RS1; +else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) + RD = 0; +else + RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2)); diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h new file mode 100644 index 0000000..c698aca --- /dev/null +++ b/riscv/insns/remu.h @@ -0,0 +1,4 @@ +if(RS2 == 0) + RD = RS1; +else + RD = sext_xprlen(zext_xprlen(RS1) % zext_xprlen(RS2)); diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h new file mode 100644 index 0000000..8234af3 --- /dev/null +++ b/riscv/insns/remuw.h @@ -0,0 +1,5 @@ +require_xpr64; +if(RS2 == 0) + RD = RS1; +else + RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2)); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h new file mode 100644 index 0000000..93c3858 --- /dev/null +++ b/riscv/insns/remw.h @@ -0,0 +1,7 @@ +require_xpr64; +if(RS2 == 0) + RD = RS1; +else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) + RD = 0; +else + RD = sext32(int32_t(RS1) % int32_t(RS2)); diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h new file mode 100644 index 0000000..af5bd10 --- /dev/null +++ b/riscv/insns/sb.h @@ -0,0 +1 @@ +mmu.store_uint8(RS1+BIMM, RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h new file mode 100644 index 0000000..2009149 --- /dev/null +++ b/riscv/insns/sd.h @@ -0,0 +1,2 @@ +require_xpr64; +mmu.store_uint64(RS1+BIMM, RS2); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h new file mode 100644 index 0000000..a484e1e --- /dev/null +++ b/riscv/insns/sh.h @@ -0,0 +1 @@ +mmu.store_uint16(RS1+BIMM, RS2); diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h new file mode 100644 index 0000000..86eb966 --- /dev/null +++ b/riscv/insns/sll.h @@ -0,0 +1 @@ +RD = sext_xprlen(RS1 << (RS2 & (xprlen-1))); diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h new file mode 100644 index 0000000..bfaf430 --- /dev/null +++ b/riscv/insns/slli.h @@ -0,0 +1,8 @@ +if(xpr64) + RD = RS1 << SHAMT; +else +{ + if(SHAMT & 0x20) + throw trap_illegal_instruction; + RD = sext32(RS1 << SHAMT); +} diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h new file mode 100644 index 0000000..1f6e50d --- /dev/null +++ b/riscv/insns/slliw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(RS1 << SHAMTW); diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h new file mode 100644 index 0000000..f3356d8 --- /dev/null +++ b/riscv/insns/sllw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(RS1 << (RS2 & 0x1F)); diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h new file mode 100644 index 0000000..5c50534 --- /dev/null +++ b/riscv/insns/slt.h @@ -0,0 +1 @@ +RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)); diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h new file mode 100644 index 0000000..1dcd892 --- /dev/null +++ b/riscv/insns/slti.h @@ -0,0 +1 @@ +RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM)); diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h new file mode 100644 index 0000000..45e579b --- /dev/null +++ b/riscv/insns/sltiu.h @@ -0,0 +1 @@ +RD = cmp_trunc(RS1) < cmp_trunc(SIMM); diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h new file mode 100644 index 0000000..2c5bdc3 --- /dev/null +++ b/riscv/insns/sltu.h @@ -0,0 +1 @@ +RD = cmp_trunc(RS1) < cmp_trunc(RS2); diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h new file mode 100644 index 0000000..7102da0 --- /dev/null +++ b/riscv/insns/sra.h @@ -0,0 +1 @@ +RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1))); diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h new file mode 100644 index 0000000..bb17d27 --- /dev/null +++ b/riscv/insns/srai.h @@ -0,0 +1,8 @@ +if(xpr64) + RD = sreg_t(RS1) >> SHAMT; +else +{ + if(SHAMT & 0x20) + throw trap_illegal_instruction; + RD = sext32(int32_t(RS1) >> SHAMT); +} diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h new file mode 100644 index 0000000..4c56730 --- /dev/null +++ b/riscv/insns/sraiw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(int32_t(RS1) >> SHAMTW); diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h new file mode 100644 index 0000000..d178374 --- /dev/null +++ b/riscv/insns/sraw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32(int32_t(RS1) >> (RS2 & 0x1F)); diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h new file mode 100644 index 0000000..8230d27 --- /dev/null +++ b/riscv/insns/srl.h @@ -0,0 +1,4 @@ +if(xpr64) + RD = RS1 >> (RS2 & 0x3F); +else + RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F)); diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h new file mode 100644 index 0000000..5378fd1 --- /dev/null +++ b/riscv/insns/srli.h @@ -0,0 +1,8 @@ +if(xpr64) + RD = RS1 >> SHAMT; +else +{ + if(SHAMT & 0x20) + throw trap_illegal_instruction; + RD = sext32((uint32_t)RS1 >> SHAMT); +} diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h new file mode 100644 index 0000000..c400507 --- /dev/null +++ b/riscv/insns/srliw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32((uint32_t)RS1 >> SHAMTW); diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h new file mode 100644 index 0000000..b206f7c --- /dev/null +++ b/riscv/insns/srlw.h @@ -0,0 +1,2 @@ +require_xpr64; +RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F)); diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h new file mode 100644 index 0000000..791a82c --- /dev/null +++ b/riscv/insns/stop.h @@ -0,0 +1,3 @@ +require_vector; +utmode = false; +throw vt_command_stop; diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h new file mode 100644 index 0000000..2b1e057 --- /dev/null +++ b/riscv/insns/sub.h @@ -0,0 +1 @@ +RD = sext_xprlen(RS1 - RS2); diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h new file mode 100644 index 0000000..28db334 --- /dev/null +++ b/riscv/insns/subw.h @@ -0,0 +1,3 @@ +require_xpr64; +RD = sext32(RS1 - RS2); + diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h new file mode 100644 index 0000000..dbe260f --- /dev/null +++ b/riscv/insns/sw.h @@ -0,0 +1 @@ +mmu.store_uint32(RS1+BIMM, RS2); diff --git a/riscv/insns/syscall.h b/riscv/insns/syscall.h new file mode 100644 index 0000000..2c7199d --- /dev/null +++ b/riscv/insns/syscall.h @@ -0,0 +1 @@ +throw trap_syscall; diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h new file mode 100644 index 0000000..b3c944c --- /dev/null +++ b/riscv/insns/utidx.h @@ -0,0 +1,2 @@ +require_vector; +RD = utidx; diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h new file mode 100644 index 0000000..7779645 --- /dev/null +++ b/riscv/insns/vf.h @@ -0,0 +1,8 @@ +require_vector; +for (int i=0; i<VL; i++) +{ + uts[i]->pc = RS1+SIMM; + uts[i]->utmode = true; + while (uts[i]->utmode) + uts[i]->step(1, false); // XXX +} diff --git a/riscv/insns/vfld.h b/riscv/insns/vfld.h new file mode 100644 index 0000000..9b40470 --- /dev/null +++ b/riscv/insns/vfld.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_LOAD(FRD, load_int64, 8); diff --git a/riscv/insns/vflsegd.h b/riscv/insns/vflsegd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vflsegd.h diff --git a/riscv/insns/vflsegstd.h b/riscv/insns/vflsegstd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vflsegstd.h diff --git a/riscv/insns/vflsegstw.h b/riscv/insns/vflsegstw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vflsegstw.h diff --git a/riscv/insns/vflsegw.h b/riscv/insns/vflsegw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vflsegw.h diff --git a/riscv/insns/vflstd.h b/riscv/insns/vflstd.h new file mode 100644 index 0000000..fa9b32d --- /dev/null +++ b/riscv/insns/vflstd.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_LOAD(FRD, load_int64, RS2); diff --git a/riscv/insns/vflstw.h b/riscv/insns/vflstw.h new file mode 100644 index 0000000..716c818 --- /dev/null +++ b/riscv/insns/vflstw.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_LOAD(FRD, load_int32, RS2); diff --git a/riscv/insns/vflw.h b/riscv/insns/vflw.h new file mode 100644 index 0000000..75fdd04 --- /dev/null +++ b/riscv/insns/vflw.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_LOAD(FRD, load_int32, 4); diff --git a/riscv/insns/vfmst.h b/riscv/insns/vfmst.h new file mode 100644 index 0000000..686d7c5 --- /dev/null +++ b/riscv/insns/vfmst.h @@ -0,0 +1,4 @@ +require_vector; +require_fp; +assert(0 <= RS2 && RS2 < MAX_UTS); +UT_FRD(RS2) = FRS1; diff --git a/riscv/insns/vfmsv.h b/riscv/insns/vfmsv.h new file mode 100644 index 0000000..a9aa876 --- /dev/null +++ b/riscv/insns/vfmsv.h @@ -0,0 +1,5 @@ +require_vector; +require_fp; +UT_LOOP_START + UT_LOOP_FRD = FRS1; +UT_LOOP_END diff --git a/riscv/insns/vfmts.h b/riscv/insns/vfmts.h new file mode 100644 index 0000000..a6da126 --- /dev/null +++ b/riscv/insns/vfmts.h @@ -0,0 +1,4 @@ +require_vector; +require_fp; +assert(0 <= RS2 && RS2 < MAX_UTS); +FRD = UT_FRS1(RS2); diff --git a/riscv/insns/vfmvv.h b/riscv/insns/vfmvv.h new file mode 100644 index 0000000..279da21 --- /dev/null +++ b/riscv/insns/vfmvv.h @@ -0,0 +1,5 @@ +require_vector; +require_fp; +UT_LOOP_START + UT_LOOP_FRD = UT_LOOP_FRS1; +UT_LOOP_END diff --git a/riscv/insns/vfsd.h b/riscv/insns/vfsd.h new file mode 100644 index 0000000..f619fc8 --- /dev/null +++ b/riscv/insns/vfsd.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_STORE(FRD, store_uint64, 8); diff --git a/riscv/insns/vfssegd.h b/riscv/insns/vfssegd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vfssegd.h diff --git a/riscv/insns/vfssegstd.h b/riscv/insns/vfssegstd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vfssegstd.h diff --git a/riscv/insns/vfssegstw.h b/riscv/insns/vfssegstw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vfssegstw.h diff --git a/riscv/insns/vfssegw.h b/riscv/insns/vfssegw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vfssegw.h diff --git a/riscv/insns/vfsstd.h b/riscv/insns/vfsstd.h new file mode 100644 index 0000000..b3bb260 --- /dev/null +++ b/riscv/insns/vfsstd.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_STORE(FRD, store_uint64, RS2); diff --git a/riscv/insns/vfsstw.h b/riscv/insns/vfsstw.h new file mode 100644 index 0000000..9cef9b0 --- /dev/null +++ b/riscv/insns/vfsstw.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_STORE(FRD, store_uint32, RS2); diff --git a/riscv/insns/vfsw.h b/riscv/insns/vfsw.h new file mode 100644 index 0000000..3fe3d3f --- /dev/null +++ b/riscv/insns/vfsw.h @@ -0,0 +1,3 @@ +require_vector; +require_fp; +VEC_STORE(FRD, store_uint32, 4); diff --git a/riscv/insns/vlb.h b/riscv/insns/vlb.h new file mode 100644 index 0000000..618380a --- /dev/null +++ b/riscv/insns/vlb.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int8, 1); diff --git a/riscv/insns/vlbu.h b/riscv/insns/vlbu.h new file mode 100644 index 0000000..f92c8b5 --- /dev/null +++ b/riscv/insns/vlbu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint8, 1); diff --git a/riscv/insns/vld.h b/riscv/insns/vld.h new file mode 100644 index 0000000..fb7a3c5 --- /dev/null +++ b/riscv/insns/vld.h @@ -0,0 +1,3 @@ +require_vector; +require_xpr64; +VEC_LOAD(RD, load_int64, 8); diff --git a/riscv/insns/vlh.h b/riscv/insns/vlh.h new file mode 100644 index 0000000..269c2a8 --- /dev/null +++ b/riscv/insns/vlh.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int16, 2); diff --git a/riscv/insns/vlhu.h b/riscv/insns/vlhu.h new file mode 100644 index 0000000..7a2019d --- /dev/null +++ b/riscv/insns/vlhu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint16, 2); diff --git a/riscv/insns/vlsegb.h b/riscv/insns/vlsegb.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegb.h diff --git a/riscv/insns/vlsegbu.h b/riscv/insns/vlsegbu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegbu.h diff --git a/riscv/insns/vlsegd.h b/riscv/insns/vlsegd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegd.h diff --git a/riscv/insns/vlsegh.h b/riscv/insns/vlsegh.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegh.h diff --git a/riscv/insns/vlseghu.h b/riscv/insns/vlseghu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlseghu.h diff --git a/riscv/insns/vlsegstb.h b/riscv/insns/vlsegstb.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegstb.h diff --git a/riscv/insns/vlsegstbu.h b/riscv/insns/vlsegstbu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegstbu.h diff --git a/riscv/insns/vlsegstd.h b/riscv/insns/vlsegstd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegstd.h diff --git a/riscv/insns/vlsegsth.h b/riscv/insns/vlsegsth.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegsth.h diff --git a/riscv/insns/vlsegsthu.h b/riscv/insns/vlsegsthu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegsthu.h diff --git a/riscv/insns/vlsegstw.h b/riscv/insns/vlsegstw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegstw.h diff --git a/riscv/insns/vlsegstwu.h b/riscv/insns/vlsegstwu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegstwu.h diff --git a/riscv/insns/vlsegw.h b/riscv/insns/vlsegw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegw.h diff --git a/riscv/insns/vlsegwu.h b/riscv/insns/vlsegwu.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vlsegwu.h diff --git a/riscv/insns/vlstb.h b/riscv/insns/vlstb.h new file mode 100644 index 0000000..219d90e --- /dev/null +++ b/riscv/insns/vlstb.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int8, RS2); diff --git a/riscv/insns/vlstbu.h b/riscv/insns/vlstbu.h new file mode 100644 index 0000000..09faa29 --- /dev/null +++ b/riscv/insns/vlstbu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint8, RS2); diff --git a/riscv/insns/vlstd.h b/riscv/insns/vlstd.h new file mode 100644 index 0000000..5e5de9c --- /dev/null +++ b/riscv/insns/vlstd.h @@ -0,0 +1,3 @@ +require_vector; +require_xpr64; +VEC_LOAD(RD, load_int64, RS2); diff --git a/riscv/insns/vlsth.h b/riscv/insns/vlsth.h new file mode 100644 index 0000000..af6b5b5 --- /dev/null +++ b/riscv/insns/vlsth.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int16, RS2); diff --git a/riscv/insns/vlsthu.h b/riscv/insns/vlsthu.h new file mode 100644 index 0000000..0fe8452 --- /dev/null +++ b/riscv/insns/vlsthu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint16, RS2); diff --git a/riscv/insns/vlstw.h b/riscv/insns/vlstw.h new file mode 100644 index 0000000..5375dc0 --- /dev/null +++ b/riscv/insns/vlstw.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int32, RS2); diff --git a/riscv/insns/vlstwu.h b/riscv/insns/vlstwu.h new file mode 100644 index 0000000..328e23f --- /dev/null +++ b/riscv/insns/vlstwu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint32, RS2); diff --git a/riscv/insns/vlw.h b/riscv/insns/vlw.h new file mode 100644 index 0000000..6e35911 --- /dev/null +++ b/riscv/insns/vlw.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_int32, 4); diff --git a/riscv/insns/vlwu.h b/riscv/insns/vlwu.h new file mode 100644 index 0000000..4fa1489 --- /dev/null +++ b/riscv/insns/vlwu.h @@ -0,0 +1,2 @@ +require_vector; +VEC_LOAD(RD, load_uint32, 4); diff --git a/riscv/insns/vmst.h b/riscv/insns/vmst.h new file mode 100644 index 0000000..f4d03d9 --- /dev/null +++ b/riscv/insns/vmst.h @@ -0,0 +1,3 @@ +require_vector; +assert(0 <= RS2 && RS2 < MAX_UTS); +UT_RD(RS2) = RS1; diff --git a/riscv/insns/vmsv.h b/riscv/insns/vmsv.h new file mode 100644 index 0000000..c6f4c2c --- /dev/null +++ b/riscv/insns/vmsv.h @@ -0,0 +1,4 @@ +require_vector; +UT_LOOP_START + UT_LOOP_RD = RS1; +UT_LOOP_END diff --git a/riscv/insns/vmts.h b/riscv/insns/vmts.h new file mode 100644 index 0000000..2d463bc --- /dev/null +++ b/riscv/insns/vmts.h @@ -0,0 +1,3 @@ +require_vector; +assert(0 <= RS2 && RS2 < MAX_UTS); +RD = UT_RS1(RS2); diff --git a/riscv/insns/vmvv.h b/riscv/insns/vmvv.h new file mode 100644 index 0000000..91d63d4 --- /dev/null +++ b/riscv/insns/vmvv.h @@ -0,0 +1,4 @@ +require_vector; +UT_LOOP_START + UT_LOOP_RD = UT_LOOP_RS1; +UT_LOOP_END diff --git a/riscv/insns/vsb.h b/riscv/insns/vsb.h new file mode 100644 index 0000000..c3d5b9d --- /dev/null +++ b/riscv/insns/vsb.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint8, 1); diff --git a/riscv/insns/vsd.h b/riscv/insns/vsd.h new file mode 100644 index 0000000..9c02069 --- /dev/null +++ b/riscv/insns/vsd.h @@ -0,0 +1,3 @@ +require_vector; +require_xpr64; +VEC_STORE(RD, store_uint64, 8); diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h new file mode 100644 index 0000000..c2212ff --- /dev/null +++ b/riscv/insns/vsetvl.h @@ -0,0 +1,3 @@ +require_vector; +setvl(RS1); +RD = VL; diff --git a/riscv/insns/vsh.h b/riscv/insns/vsh.h new file mode 100644 index 0000000..623eda8 --- /dev/null +++ b/riscv/insns/vsh.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint16, 2); diff --git a/riscv/insns/vssegb.h b/riscv/insns/vssegb.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegb.h diff --git a/riscv/insns/vssegd.h b/riscv/insns/vssegd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegd.h diff --git a/riscv/insns/vssegh.h b/riscv/insns/vssegh.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegh.h diff --git a/riscv/insns/vssegstb.h b/riscv/insns/vssegstb.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegstb.h diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegstd.h diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegsth.h diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegstw.h diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vssegw.h diff --git a/riscv/insns/vsstb.h b/riscv/insns/vsstb.h new file mode 100644 index 0000000..b83cc50 --- /dev/null +++ b/riscv/insns/vsstb.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint8, RS2); diff --git a/riscv/insns/vsstd.h b/riscv/insns/vsstd.h new file mode 100644 index 0000000..26868d2 --- /dev/null +++ b/riscv/insns/vsstd.h @@ -0,0 +1,3 @@ +require_vector; +require_xpr64; +VEC_STORE(RD, store_uint64, RS2); diff --git a/riscv/insns/vssth.h b/riscv/insns/vssth.h new file mode 100644 index 0000000..3904331 --- /dev/null +++ b/riscv/insns/vssth.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint16, RS2); diff --git a/riscv/insns/vsstw.h b/riscv/insns/vsstw.h new file mode 100644 index 0000000..8f05953 --- /dev/null +++ b/riscv/insns/vsstw.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint32, RS2); diff --git a/riscv/insns/vsw.h b/riscv/insns/vsw.h new file mode 100644 index 0000000..662d4e3 --- /dev/null +++ b/riscv/insns/vsw.h @@ -0,0 +1,2 @@ +require_vector; +VEC_STORE(RD, store_uint32, 4); diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/riscv/insns/vtcfgivl.h diff --git a/riscv/insns/vvcfgivl.h b/riscv/insns/vvcfgivl.h new file mode 100644 index 0000000..0ded9f8 --- /dev/null +++ b/riscv/insns/vvcfgivl.h @@ -0,0 +1,6 @@ +require_vector; +nxpr_use = SIMM & 0x3f; +nfpr_use = (SIMM >> 6) & 0x3f; +vcfg(); +setvl(RS1); +RD = VL; diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h new file mode 100644 index 0000000..49b1783 --- /dev/null +++ b/riscv/insns/xor.h @@ -0,0 +1 @@ +RD = RS1 ^ RS2; diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h new file mode 100644 index 0000000..5852aac --- /dev/null +++ b/riscv/insns/xori.h @@ -0,0 +1 @@ +RD = SIMM ^ RS1; |