diff options
-rw-r--r-- | customext/dummy_rocc.cc | 2 | ||||
-rw-r--r-- | disasm/disasm.cc | 6 | ||||
-rw-r--r-- | riscv/cachesim.h | 5 | ||||
-rw-r--r-- | riscv/csrs.cc | 6 | ||||
-rw-r--r-- | riscv/csrs.h | 2 | ||||
-rw-r--r-- | riscv/entropy_source.h | 3 | ||||
-rw-r--r-- | riscv/execute.cc | 2 | ||||
-rw-r--r-- | riscv/extension.h | 2 | ||||
-rw-r--r-- | riscv/insns/amoswap_d.h | 2 | ||||
-rw-r--r-- | riscv/insns/amoswap_w.h | 2 | ||||
-rw-r--r-- | riscv/mmu.cc | 2 | ||||
-rw-r--r-- | riscv/mmu.h | 4 | ||||
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/processor.h | 2 | ||||
-rw-r--r-- | riscv/rocc.cc | 2 | ||||
-rw-r--r-- | riscv/rom.cc | 2 | ||||
-rw-r--r-- | riscv/tracer.h | 2 | ||||
-rw-r--r-- | riscv/triggers.cc | 2 | ||||
-rw-r--r-- | riscv/v_ext_macros.h | 4 |
19 files changed, 28 insertions, 26 deletions
diff --git a/customext/dummy_rocc.cc b/customext/dummy_rocc.cc index 85ab7aa..5afa56a 100644 --- a/customext/dummy_rocc.cc +++ b/customext/dummy_rocc.cc @@ -7,7 +7,7 @@ class dummy_rocc_t : public rocc_t public: const char* name() { return "dummy_rocc"; } - reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2) + reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t UNUSED xs2) { reg_t prev_acc = acc[insn.rs2]; diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 7bb3ec0..1d7c6d5 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -180,7 +180,7 @@ struct : public arg_t { } rvc_fp_rs2s; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return xpr_name[X_SP]; } } rvc_sp; @@ -314,7 +314,7 @@ struct : public arg_t { } vm; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return "v0"; } } v0; @@ -358,7 +358,7 @@ struct : public arg_t { } v_vtype; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return "x0"; } } x0; diff --git a/riscv/cachesim.h b/riscv/cachesim.h index b7f9014..d7046f9 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -4,6 +4,7 @@ #define _RISCV_CACHE_SIM_H #include "memtracer.h" +#include "common.h" #include <cstring> #include <string> #include <map> @@ -108,7 +109,7 @@ class icache_sim_t : public cache_memtracer_t { public: icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {} - bool interested_in_range(uint64_t begin, uint64_t end, access_type type) + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) { return type == FETCH; } @@ -122,7 +123,7 @@ class dcache_sim_t : public cache_memtracer_t { public: dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {} - bool interested_in_range(uint64_t begin, uint64_t end, access_type type) + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) { return type == LOAD || type == STORE; } diff --git a/riscv/csrs.cc b/riscv/csrs.cc index c8f8c8a..93b0bae 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -60,7 +60,7 @@ void csr_t::log_write() const noexcept { log_special_write(address, written_value()); } -void csr_t::log_special_write(const reg_t address, const reg_t val) const noexcept { +void csr_t::log_special_write(const reg_t UNUSED address, const reg_t UNUSED val) const noexcept { #if defined(RISCV_ENABLE_COMMITLOG) proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0}; #endif @@ -1023,7 +1023,7 @@ reg_t const_csr_t::read() const noexcept { return val; } -bool const_csr_t::unlogged_write(const reg_t val) noexcept { +bool const_csr_t::unlogged_write(const reg_t UNUSED val) noexcept { return false; } @@ -1466,7 +1466,7 @@ reg_t scountovf_csr_t::read() const noexcept { return val; } -bool scountovf_csr_t::unlogged_write(const reg_t val) noexcept { +bool scountovf_csr_t::unlogged_write(const reg_t UNUSED val) noexcept { /* this function is unused */ return false; } diff --git a/riscv/csrs.h b/riscv/csrs.h index 1cc2d74..70fa2f4 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -521,7 +521,7 @@ class time_counter_csr_t: public csr_t { void sync(const reg_t val) noexcept; protected: - virtual bool unlogged_write(const reg_t val) noexcept override { return false; }; + virtual bool unlogged_write(const reg_t UNUSED val) noexcept override { return false; }; private: reg_t shadow_val; }; diff --git a/riscv/entropy_source.h b/riscv/entropy_source.h index c2ee2c4..3a3c8e6 100644 --- a/riscv/entropy_source.h +++ b/riscv/entropy_source.h @@ -3,6 +3,7 @@ #include <iostream> #include "internals.h" +#include "common.h" // // Used to model the cryptography extension entropy source. @@ -30,7 +31,7 @@ public: // seed register // ------------------------------------------------------------ - void set_seed(reg_t val) { + void set_seed(reg_t UNUSED val) { // Always ignore writes to seed. // This CSR is strictly read only. It occupies a RW CSR address // to handle the side-effect of the changing seed value on a read. diff --git a/riscv/execute.cc b/riscv/execute.cc index 36621ca..5d24ce8 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -156,7 +156,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } #endif -inline void processor_t::update_histogram(reg_t pc) +inline void processor_t::update_histogram(reg_t UNUSED pc) { #ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; diff --git a/riscv/extension.h b/riscv/extension.h index d1e847d..de6ece3 100644 --- a/riscv/extension.h +++ b/riscv/extension.h @@ -15,7 +15,7 @@ class extension_t virtual std::vector<disasm_insn_t*> get_disasms() = 0; virtual const char* name() = 0; virtual void reset() {}; - virtual void set_debug(bool value) {}; + virtual void set_debug(bool UNUSED value) {} virtual ~extension_t(); void set_processor(processor_t* _p) { p = _p; } diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h index e1bffde..f9188ea 100644 --- a/riscv/insns/amoswap_d.h +++ b/riscv/insns/amoswap_d.h @@ -1,3 +1,3 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t UNUSED lhs) { return RS2; })); diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h index 0f78369..151f095 100644 --- a/riscv/insns/amoswap_w.h +++ b/riscv/insns/amoswap_w.h @@ -1,2 +1,2 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t UNUSED lhs) { return RS2; }))); diff --git a/riscv/mmu.cc b/riscv/mmu.cc index d0a55f0..1028026 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -114,7 +114,7 @@ reg_t reg_from_bytes(size_t len, const uint8_t* bytes) abort(); } -bool mmu_t::mmio_ok(reg_t addr, access_type type) +bool mmu_t::mmio_ok(reg_t addr, access_type UNUSED type) { // Disallow access to debug region when not in debug mode if (addr >= DEBUG_START && addr <= DEBUG_END && proc && !proc->state.debug_mode) diff --git a/riscv/mmu.h b/riscv/mmu.h index ca8b792..1cd614b 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -52,7 +52,7 @@ public: #define RISCV_XLATE_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) - inline reg_t misaligned_load(reg_t addr, size_t size, uint32_t xlate_flags) + inline reg_t misaligned_load(reg_t addr, size_t UNUSED size, uint32_t xlate_flags) { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; @@ -72,7 +72,7 @@ public: #endif } - inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags, bool actually_store=true) + inline void misaligned_store(reg_t addr, reg_t UNUSED data, size_t UNUSED size, uint32_t xlate_flags, bool UNUSED actually_store=true) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) { diff --git a/riscv/processor.cc b/riscv/processor.cc index 5ae6bbb..9bb7d04 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -960,7 +960,7 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) throw trap_illegal_instruction(insn.bits()); } -reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) +reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc) { // The illegal instruction can be longer than ILEN bits, where the tval will // contain the first ILEN bits of the faulting instruction. We hard-code the diff --git a/riscv/processor.h b/riscv/processor.h index 441e522..fc80914 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -401,7 +401,7 @@ public: // vector element for varies SEW template<class T> - T& elt(reg_t vReg, reg_t n, bool is_write = false) { + T& elt(reg_t vReg, reg_t n, bool UNUSED is_write = false) { assert(vsew != 0); assert((VLEN >> 3)/sizeof(T) > 0); reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); diff --git a/riscv/rocc.cc b/riscv/rocc.cc index f50934f..f0dd0b2 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -18,7 +18,7 @@ return pc+4; \ } \ \ - reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \ + reg_t rocc_t::custom##n(rocc_insn_t UNUSED insn, reg_t UNUSED xs1, reg_t UNUSED xs2) \ { \ illegal_instruction(); \ return 0; \ diff --git a/riscv/rom.cc b/riscv/rom.cc index b852862..2d10e91 100644 --- a/riscv/rom.cc +++ b/riscv/rom.cc @@ -13,7 +13,7 @@ bool rom_device_t::load(reg_t addr, size_t len, uint8_t* bytes) return true; } -bool rom_device_t::store(reg_t addr, size_t len, const uint8_t* bytes) +bool rom_device_t::store(reg_t UNUSED addr, size_t UNUSED len, const uint8_t UNUSED *bytes) { return false; } diff --git a/riscv/tracer.h b/riscv/tracer.h index 9f1bc78..d74edae 100644 --- a/riscv/tracer.h +++ b/riscv/tracer.h @@ -5,7 +5,7 @@ #include "processor.h" -static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) { +static inline void trace_opcode(processor_t UNUSED *p, insn_bits_t UNUSED opc, insn_t UNUSED insn) { } #endif diff --git a/riscv/triggers.cc b/riscv/triggers.cc index ef05551..390ebe4 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -62,7 +62,7 @@ bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep return true; } -reg_t mcontrol_t::tdata2_read(const processor_t * const proc) const noexcept { +reg_t mcontrol_t::tdata2_read(const processor_t UNUSED * const proc) const noexcept { return tdata2; } diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index afc4837..4696343 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1410,14 +1410,14 @@ reg_t index[P.VU.vlmax]; \ switch (P.VU.vsew) { \ case e32: { \ auto vs3 = P.VU.elt< type ## 32_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint32(baseAddr + index[i], [&](type ## 32_t lhs) { op }); \ + auto val = MMU.amo_uint32(baseAddr + index[i], [&](type ## 32_t UNUSED lhs) { op }); \ if (insn.v_wd()) \ P.VU.elt< type ## 32_t>(vd, vreg_inx, true) = val; \ } \ break; \ case e64: { \ auto vs3 = P.VU.elt< type ## 64_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint64(baseAddr + index[i], [&](type ## 64_t lhs) { op }); \ + auto val = MMU.amo_uint64(baseAddr + index[i], [&](type ## 64_t UNUSED lhs) { op }); \ if (insn.v_wd()) \ P.VU.elt< type ## 64_t>(vd, vreg_inx, true) = val; \ } \ |